Rapidus has finished construction of its IIM-1 fab in Chitose, with tooling installed, operational, and now in the process testing phase that builds the data set behind a PDK. Futurum examines whether the RAADS agentic design platform built with Cadence and privileged access to IBM transistor IP will make the Rapidus 2nm foundry the fastest, most flexible route to an inference accelerator tapeout.
What Is Covered in This Article:
IIM-1 construction complete, tooling installed and operational, process testing underway
An initial PDK release and first customer design starts on the path to 2027 production
RAADS predictor with Cadence InnoStack AI Super Agent targeting up to a 2X design turnaround gain [1]
Commercialized IBM 2nm gate-all-around transistor IP and a licensed path toward IBM’s NanoStack CFET
Competitive positioning against TSMC N2, Intel 18A, and Samsung SF2 for inference accelerator tapeouts
The News: Rapidus has completed construction of its IIM-1 fab in Chitose, Hokkaido, finished installing its production tooling, and entered the process testing phase, Futurum learned in a briefing. ASML lithography systems are under test, packaging pilot lines are running, and wafers are moving through the line to characterize transistors and build the data set behind a Process Design Kit. The update follows the joint announcement of Rapidus and Cadence that Cadence’s InnoStack AI Super Agent will be integrated into RAADS, the Rapidus AI-Agentic Design Solution, targeting up to a 2X improvement in design turnaround time.
‘By integrating with Cadence’s InnoStack AI Super Agent, we strengthen our design environment to help customers manage increasing SoC complexity and realize full value of Rapidus’ advanced process technologies,’ said Dr. Atsuyoshi Koike, Representative Director and CEO of Rapidus.
Rapidus’ IIM-1 Fab Construction is Completed. Will Cadence Make It the First Agentic Foundry?
Analyst Take: The Rapidus 2nm foundry has crossed the line separating a construction project from a manufacturing company. The IIM-1 building in Chitose is finished, staffed, and the toolset is installed and operating, per Futurum’s briefing. Testing has shifted from individual machines to the movement of wafers between them, the step that generates the process data a PDK is built from. The flexibility architecture Rapidus has described since 2023 is now realized with fully single-wafer front-end processing, a ceiling-mounted grid transport system in place of the linear raceway, packaging pilot lines in operation, and an agentic design platform co-developed with Cadence. Futurum’s view is that Rapidus has assembled the most flexibility-optimized advanced foundry to achieve fast tapeout economics for inference accelerators.
A Finished IIM-1 Makes the Rapidus 2nm Foundry an Operating Company
The physical milestone matters because Rapidus is building everything at once. The current test regime covers how wafers move from machine to machine, how many layers each process can produce, and how yield behaves on early 2nm gate-all-around transistors. The sequence precipitates an early PDK release, opens initial design work, triggers a commercial-strength release, and production begins once customers complete design-in against the company’s 2027 mass production target.
The corporate structure matured alongside the cleanroom. Rapidus now counts 32 private companies as investors, and the latest Japanese government funding came as a capital investment through the Information-Technology Promotion Agency, which converts the state from grant-maker to shareholder. Our briefing put the totals at roughly $1 billion in private equity and roughly $10 billion in government equity, figures consistent with the ¥424.95 billion in stated capital Rapidus disclosed in June. For a company industrializing its own transistor, that is a lean operation, which is why Rapidus extends its R&D through IBM, CEA-Leti, Fraunhofer, and imec rather than building every capability in Hokkaido.
Single-Wafer Processing Aims at the Tapeout Economics of Inference Silicon
Our view of Rapidus’ case for product-market fit inference accelerators starts with the yield ramp. At mature nodes, foundries took 3 to 6 months to reach commercial yield after a tapeout. The industry now takes about a year at advanced nodes because die sizes, transistor density, and interconnect complexity have grown while batch processing limits the sample points available for tuning. Rapidus is running every front-end step single-wafer so each of the first wafers becomes an adjustment opportunity, targeting a return to the 3-to-6-month ramp. The economics behind that goal are stark at advanced-node wafer prices of $20,000 to $30,000 with a stated operational goal is a 50% reduction in total turnaround time. The testing phase now underway will convert these company targets into data.
We believe this model could be particularly well-suited for model-tuned inference accelerators. Design variation is expanding beyond speed binning into memory-to-logic ratios, I/O configurations, and inference profiles tuned for high-throughput serving or for data-heavy, low-computation workloads. Futurum observed that AMD’s portfolio fragmented into workload-specific parts, and its acquisition of Taalas added hardcoded inference silicon with a two-month tapeout cadence. A foundry that can run many small projects concurrently, with a transport grid that routes each wafer on its own path, fits that market. Capacity is the constraint on the other side of the ledger. The capital planning of foundry companies limits the available wafers to the inference build-out. Rapidus is entering into a seller’s market in which flexibility can command a premium.
RAADS Turns Agentic Design Into a Customer Acquisition Tool
The Cadence partnership gives the flexibility argument a front end. InnoStack AI Super Agent is Cadence’s agentic design orchestration technology, a supervisory AI layer that automates and coordinates the tasks in an SoC flow from early architectural exploration through implementation and signoff, applying data-driven optimization across the design lifecycle. RAADS integrates InnoStack as its orchestration core and adds Rapidus quality assurance agents, branded Navigator and Indicator, that support designers in resolving design issues. The headline claim is up to a 2X improvement in design turnaround time over traditional flows.
The most commercially interesting component is the RAADS predictor. A customer with an existing design at 7nm, 5nm, or 4nm can receive a synthetic design translated to Rapidus 2nm gate-all-around, along with predicted power, performance, and area boundaries, before committing to a full PDK-based design. The tool is slated to launch alongside the production PDK and is built partly on licensed Cadence technology, including the InnoStack agents. Rapidus is using agentic AI to attack the decision risk that protects incumbent foundries. A credible PPA forecast lowers the cost of considering a challenger fab from a full design study to a data exchange. Futurum’s coverage of CadenceLIVE 2026 and of the autonomous design demonstrations at DAC found the EDA vendors racing to sell this capability broadly, so exclusivity will erode. Rapidus is the first foundry to productize agentic prediction as a design flow, and Synopsys likely supplies much of its foundational foundry IP, which keeps the design ecosystem multi-vendor.
IBM Transistor IP Gives Rapidus a Roadmap Past the 2nm Window
The transistor franchise is the second half of the headline question. The 2nm gate-all-around device Rapidus licensed from IBM has moved from research deliverable to commercial product, with Rapidus adding its own IP to make the process manufacturable. That progression matters more after June, when IBM disclosed its NanoStack staggered CFET architecture for a sub-1nm-class node, claiming 50% logic area scaling versus 2nm and 50% performance improvement at iso-power, on a horizon IBM places about 5 years out. The Albany partnership gives Rapidus a working relationship with the research organization that has now defined two consecutive transistor generations, and the joint engineering model that industrialized the 2nm device is repeatable for CFET. IBM has licensed its technology to others before, and nothing disclosed so far grants Rapidus exclusivity on NanoStack, so the advantage is a head start rather than a moat.
Incumbents Contest the Flexibility Title With Capacity Rapidus Lacks
The competitive field defines what ‘most flexible’ has to beat. TSMC’s CyberShuttle multi-project wafer service remains the default path for small-volume advanced-node experiments. Shuttle schedules subordinate small customers to the mask timing of large ones, a constraint that Rapidus’s dedicated single-wafer flow removes. Intel ramped 18A with RibbonFET and PowerVia for internal products first, and its external foundry adoption remains thin, which makes Intel the incumbent most likely to copy a fast-turnaround, startup-friendly posture as 14A approaches with high-NA EUV. Samsung’s SF2 continues to fight yield stability perceptions, and its $16.5 billion Tesla AI6 agreement shows the price a memory-rich conglomerate will pay to anchor an inference-adjacent logic customer. Each incumbent can quote capacity Rapidus cannot.
Rapidus also competes against its own to-do list. The ERP and order-tracking infrastructure customers expect from TSMC is being written from scratch. The PDK does not yet exist in shippable form. Yield on 2nm gate-all-around is unproven, high-NA lithography economics are unproven, and the 2X design turnaround claim is unproven. The Rapidus 2nm foundry has built the most convincing flexibility architecture in the industry. Between now and 2027 mass production, it has to convert that architecture into signed design starts.
What to Watch:
Whether the PDK reaches early design customers ahead of the 2027 production target
Whether Rapidus names a first inference accelerator design customer
Whether early yield data supports the 3-to-6-month ramp target for single-wafer processing
Whether the RAADS predictor launches with the production PDK and produces PPA forecasts that customers can validate
Whether TSMC, Intel, or Samsung answer with dedicated fast-turnaround services for low-volume advanced-node customers
Read the full partnership announcement on agentic AI for advanced SoC design on the Rapidus website.
Sources
Rapidus and Cadence Partner on Agentic AI for Advanced SoC Design
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Other Insights From Futurum:
Cadence AuraStack Extends Agentic Leadership Toward Advanced Packaging Design
Cadence and Synopsys Accelerate Agentic EDA Race at Computex
Brendan is Research Director, Semiconductors, Supply Chain, and Emerging Tech. He advises clients on strategic initiatives and leads the Futurum Semiconductors Practice. He is an experienced tech industry analyst who has guided tech leaders in identifying market opportunities spanning edge processors, generative AI applications, and hyperscale data centers.
Before joining Futurum, Brendan consulted with global AI leaders and served as a Senior Analyst in Emerging Technology Research at PitchBook. At PitchBook, he developed market intelligence tools for AI, highlighted by one of the industry’s most comprehensive AI semiconductor market landscapes encompassing both public and private companies. He has advised Fortune 100 tech giants, growth-stage innovators, global investors, and leading market research firms. Before PitchBook, he led research teams in tech investment banking and market research.
Brendan is based in Seattle, Washington. He has a Bachelor of Arts Degree from Amherst College.