Lecun, Y., Bengio, Y. & Hinton, G. Deep learning. Nature 521, 436–444 (2015).
Krizhevsky, A., Sutskever, I. & Hinton, G. E. ImageNet classification with deep convolutional neural networks. Adv. Neural Inf. Process. Syst. 25, 1097–1105 (2012).
Vaswani, A. et al. Attention is all you need. In Proc. 31st Conference on Neural Information Processing Systems (NeurIPS, 2017).
Zou, X., Xu, S., Chen, X., Yan, L. & Han, Y. Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology. Sci. China Inf. Sci. 64, 1–10 (2021).
Gholami, A. et al. AI and memory wall. IEEE Micro 44, 33–39 (2024).
Seok, H. et al. Beyond von Neumann architecture: brain-inspired artificial neuromorphic devices and integrated computing. Adv. Electron. Mater. 10, 2300839 (2024).
Ganguly, A., Muralidhar, R. & Singh, V. Towards energy efficient non-von Neumann architectures for deep learning. In Proc. International Symposium on Quality Electronic Design 335–342 (IEEE, 2019).
Upadhyay, N. K. et al. Emerging memory devices for neuromorphic computing. Adv. Mater. Technol. 4, 1800589 (2019).
Rajendran, B. & Alibart, F. Neuromorphic computing based on emerging memory technologies. IEEE J. Emerg. Sel. Top. Circuits Syst. 6, 198–211 (2016).
Mannocci, P. et al. In-memory computing with emerging memory devices: status and outlook. APL Mach. Learn. 1, 010902 (2023).
Sun, X. & Yu, S. Impact of non-ideal characteristics of resistive synaptic devices on implementing convolutional neural networks. IEEE J. Emerg. Sel. Top. Circuits Syst. 9, 570–579 (2019).
Chen, P.-Y. et al. Mitigating effects of non-ideal synaptic device characteristics for on-chip learning. In Proc. 2015 IEEE/ACM International Conference on Computer-Aided Design 194–199 (IEEE, 2016).
Burr, G. W. et al. Recent progress in phase-change memory technology. IEEE J. Emerg. Sel. Top. Circuits Syst. 6, 146–162 (2016).
Ielmini, D. & Pedretti, G. Resistive switching random-access memory (RRAM): applications and requirements for memory and computing. Chem. Rev. 125, 5584–5625 (2025).
Sengupta, A. & Roy, K. Encoding neural and synaptic functionalities in electron spin: a pathway to efficient neuromorphic computing. Appl. Phys. Rev. 4, 41105 (2017).
Kim, K., Song, M. S., Hwang, H., Hwang, S. & Kim, H. A comprehensive review of advanced trends: from artificial synapses to neuromorphic systems with consideration of non-ideal effects. Front. Neurosci. 18, 1279708 (2024).
Islam, R. et al. Device and materials requirements for neuromorphic computing. J. Phys. D Appl. Phys. 52, 113001 (2019).
Chen, B. et al. Efficient in-memory computing architecture based on crossbar arrays. In Proc. 2015 IEEE International Electron Devices Meeting 17.5.1–17.5.4 (IEEE, 2015).
Hur, J. et al. Nonvolatile capacitive crossbar array for in-memory computing. Adv. Intell. Syst. 4, 2100258 (2022).
Luo, Y. C. et al. Experimental demonstration of non-volatile capacitive crossbar array for in-memory computing. In Proc. 2021 IEEE International Electron Devices Meeting 1–4 (IEEE, 2021).
Wang, C. et al. Scalable massively parallel computing using continuous-time data representation in nanoscale crossbar array. Nat. Nanotechnol. 16, 1079–1085 (2021).
Huang, Y., Ravichandran, V., Zhao, W. & Xia, Q. Towards energy-efficient computing hardware based on memristive nanodevices. IEEE Nanotechnol. Mag. 17, 30–38 (2023).
Rumelhart, D. E., Hinton, G. E. & Williams, R. J. Learning representations by back-propagating errors. Nature 323, 533–536 (1986).
Ruder, S. An overview of gradient descent optimization algorithms. ruder.io https://www.ruder.io/optimizing-gradient-descent/ (2016).
Hu, R. et al. Investigation of resistive switching mechanisms in Ti/TiOx/Pd-based RRAM devices. Adv. Electron. Mater. 8, 2100827 (2022).
Duan, Y. et al. In-depth understanding of physical mechanism of the gradual switching in AlOxNy-based RRAM as memory and synapse device. Appl. Phys. Lett. 120, 263504 (2022).
Spiga, S., Sebastian, A., Querlioz, D. & Rajendran, B. in Memristive Devices for Brain-Inspired Computing: From Materials, Devices, and Circuits to Applications — Computational Memory, Deep Learning, and Spiking Neural Networks 3–16 (Elsevier, 2020).
Agarwal, S. et al. Resistive memory device requirements for a neural algorithm accelerator. In Proc. International Joint Conference on Neural Networks 929–938 (IEEE, 2016).
Jang, J. W., Park, S., Burr, G. W., Hwang, H. & Jeong, Y. H. Optimization of conductance change in Pr1−xCaxMnO3-based synaptic devices for neuromorphic systems. IEEE Electron. Device Lett. 36, 457–459 (2015).
Ge, R. et al. Atomristor: nonvolatile resistance switching in atomic sheets of transition metal dichalcogenides. Nano Lett. 18, 434–441 (2017).
Yang, S. J. et al. Giant memory window performance and low power consumption of hexagonal boron nitride monolayer atomristor. npj 2D Mater. Appl. 9, 9 (2025).
Khan, A. I. et al. Ultralow-switching current density multilevel phase-change memory on a flexible substrate. Science 373, 1243–1247 (2021).
Liu, B. et al. Multi-level phase-change memory with ultralow power consumption and resistance drift. Sci. Bull. 66, 2217–2224 (2021).
Zhou, Y., Zhang, W., Ma, E. & Deringer, V. L. Device-scale atomistic modelling of phase-change memory materials. Nat. Electron. 6, 746–754 (2023).
Wang, K. L., Alzate, J. G. & Khalili Amiri, P. Low-power non-volatile spintronic memory: STT-RAM and beyond. J. Phys. D 46, 074003 (2013).
Ramaswamy, R., Lee, J. M., Cai, K. & Yang, H. Recent advances in spin–orbit torques: moving towards device applications. Appl. Phys. Rev. 5, 031107 (2018).
Siddiqui, S. A. et al. Magnetic domain wall based synaptic and activation function generator for neuromorphic accelerators. Nano Lett. 20, 1033–1040 (2019).
Raymenants, E. et al. Chain of magnetic tunnel junctions as a spintronic memristor. J. Appl. Phys. 124, 152116 (2018).
Ross, A. et al. Multilayer spintronic neural networks with radiofrequency connections. Nat. Nanotechnol. 18, 1273–1280 (2023).
Liu, L. et al. Domain wall magnetic tunnel junction-based artificial synapses and neurons for all-spin neuromorphic hardware. Nat. Commun. 15, 4534 (2024).
Hassan, N. et al. Magnetic domain wall neuron with lateral inhibition. J. Appl. Phys. 124, 152127 (2018).
Durner, C. A., Migliorini, A., Jeon, J. C. & Parkin, S. S. P. Reconfigurable magnetic inhibitor for domain wall logic and neuronal devices. ACS Nano 19, 5316–5325 (2025).
Vakili, H. et al. Skyrmionics — computing and memory technologies based on topological excitations in magnets. J. Appl. Phys. 130, 70908 (2021).
da Câmara Santa Clara Gomes, T. et al. Neuromorphic weighted sums with magnetic skyrmions. Nat. Electron. 8, 204–214 (2025).
Chai, X. et al. Nonvolatile ferroelectric field-effect transistors. Nat. Commun. 11, 2811 (2020).
Mulaosmanovic, H. et al. Ferroelectric field-effect transistors based on HfO2: a review. Nanotechnology 32, 502002 (2021).
Yu, E., Gaurav Kumar, K., Saxena, U. & Roy, K. Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads. Sci. Rep. 14, 9426 (2024).
Luo, J. D. et al. Ferroelectric undoped HfOx capacitor with symmetric synaptic for neural network accelerator. IEEE Trans. Electron Devices 68, 1374–1377 (2021).
Cao, R. et al. Improvement of endurance in HZO-based ferroelectric capacitor using Ru electrode. IEEE Electron. Device Lett. 40, 1744–1747 (2019).
Fouda, M. E., Neftci, E., Eltawil, A. & Kurdahi, F. Effect of asymmetric nonlinearity dynamics in RRAMs on spiking neural network performance. In Proc. Asilomar Conference on Signals, Systems, and Computers 495–499 (IEEE, 2019).
Onen, M. et al. Neural network training with asymmetric crosspoint elements. Front. Artif. Intell. 5, 891624 (2022).
Balatti, S. et al. Understanding pulsed-cycling variability and endurance in HfOx RRAM. In Proc. 2015 IEEE International Reliability Physics Symposium 5B31–5B36 (IEEE, 2015).
Garg, C. et al. Impact of random spatial fluctuation in non-uniform crystalline phases on the device variation of ferroelectric FET. IEEE Electron. Device Lett. 42, 1160–1163 (2021).
Bin Hamid, S. & Zunaid Baten, M. Impact of process variation in spin–orbit torque-based magnetic tunnel junctions on the performance of spiking neural networks. IEEE Trans. Electron Devices 71, 6672–6679 (2024).
Ni, K. et al. Impact of extrinsic variation sources on the device-to-device variation in ferroelectric FET. In Proc. 2020 IEEE International Reliability Physics Symposium 1–5 (IEEE, 2020).
Resch, S. et al. On endurance of processing in (nonvolatile) memory. In Proc. 50th Annual International Symposium on Computer Architecture 1–13 (Association for Computing Machinery, 2023).
Gong, N. & Ma, T. P. A study of endurance issues in HfO2-based ferroelectric field effect transistors: charge trapping and trap generation. IEEE Electron. Device Lett. 39, 15–18 (2018).
Li, J., Luan, B. & Lam, C. Resistance drift in phase change memory. In Proc. 2012 IEEE International Reliability Physics Symposium 6C.1.1–6C.1.6 (IEEE, 2012).
Baroni, A. et al. Low conductance state drift characterization and mitigation in resistive switching memories (RRAM) for artificial neural networks. IEEE Trans. Device Mater. Reliab. 22, 340–347 (2022).
Sun, D. et al. Uniformity, linearity, and symmetry enhancement in TiOx/MoS2−xOx based analog RRAM via S-vacancy confined nanofilament. Nano Lett. 24, 16283–16292 (2024).
Liao, Y. et al. A compact model of analog RRAM with device and array nonideal effects for neuromorphic systems. IEEE Trans. Electron Devices 67, 1593–1599 (2020).
Pedretti, G., Ambrosi, E. & Ielmini, D. Conductance variations and their impact on the precision of in-memory computing with resistive switching memory (RRAM). In Proc. 2021 IEEE International Reliability Physics Symposium 1–8 (IEEE, 2021).
Degraeve, R. et al. Causes and consequences of the stochastic aspect of filamentary RRAM. Microelectron. Eng. 147, 171–175 (2015).
Zhao, M. et al. Investigation of statistical retention of filamentary analog RRAM for neuromorphic computing. In Proc. 2017 IEEE International Electron Devices Meeting 39.4.1–39.4.4 (IEEE, 2018).
Zhao, M. et al. Endurance and retention degradation of intermediate levels in filamentary analog RRAM. IEEE J. Electron Devices Soc. 7, 1239–1247 (2019).
Moon, K. et al. Bidirectional non-filamentary RRAM as an analog neuromorphic synapse, Part I: Al/Mo/Pr0.7Ca0.3MnO3 material improvements and device measurements. IEEE J. Electron Devices Soc. 6, 146–155 (2018).
Fatheema, J., Liang, L., Lee, B. H., Wang, W. & Akinwande, D. First-principles investigation of the resistive switching energetics in monolayer MoS2: insights into metal diffusion and adsorption. npj 2D Mater. Appl. 9, 74 (2025).
Yang, S. J., Gu, Y. & Akinwande, D. Multifunctional resistance switching in monolayer hexagonal boron nitride atomristor. In Proc. 2023 Device Research Conference 1–2 (IEEE, 2023).
Nandakumar, S. R. et al. A phase-change memory model for neuromorphic computing. J. Appl. Phys. 124, 152135 (2018).
Boybat, I. et al. Neuromorphic computing with multi-memristive synapses. Nat. Commun. 9, 2514 (2018).
Syed, G. S., Le Gallo, M. & Sebastian, A. Phase-change memory for in-memory computing. Chem. Rev. 125, 5163–5194 (2025).
Kumari, S., Durai, S. & Manivannan, A. Impact of process-induced variability on multi-bit phase change memory devices. Microelectron. J. 130, 105638 (2022).
Zhang, W. & Li, T. Characterizing and mitigating the impact of process variations on phase change based memory systems. In Proc. 42nd Annual IEEE/ACM International Symposium on Microarchitecture 2–13 (Association for Computing Machinery, 2009).
Wu, B. et al. Electronic mechanism for resistance drift in phase-change memory materials: link to persistent photoconductivity. J. Phys. D Appl. Phys. 53, 214002 (2020).
Wu, X. et al. Understanding interface-controlled resistance drift in superlattice phase change memory. IEEE Electron Device Lett. 43, 1669–1672 (2022).
Balatti, S. et al. Pulsed cycling operation and endurance failure of metal–oxide resistive (RRAM). In Proc. 2014 IEEE International Electron Devices Meeting 14.3.1–14.3.4 (IEEE, 2015).
Swaidan, Z., Kanj, R., El Hajj, J., Saad, E. & Kurdahi, F. RRAM endurance and retention: challenges, opportunities and implications on reliable design. In Proc. 2019 26th IEEE International Conference on Electronics, Circuits and Systems 402–405 (IEEE, 2019).
Kim, S. B., Burr, G. W., Kim, W. & Nam, S. W. Phase-change memory cycling endurance. MRS Bull. 44, 710–714 (2019).
Safranski, C. et al. Demonstration of nanosecond operation in stochastic magnetic tunnel junctions. Nano Lett. 21, 2040–2045 (2021).
Finocchio, G. et al. The promise of spintronics for unconventional computing. J. Magn. Magn. Mater. 521, 167506 (2021).
Kläui, M. et al. Domain wall pinning and controlled magnetic switching in narrow ferromagnetic ring structures with notches (invited). J. Appl. Phys. 93, 7885–7890 (2003).
De Araujo, C. I. L. et al. Investigation of domain wall pinning by square anti-notches and its application in three terminals MRAM. Appl. Phys. Lett. 114, 212403 (2019).
Jenkins, S. et al. Magnetic stray fields in nanoscale magnetic tunnel junctions. J. Phys. D Appl. Phys. 53, 044001 (2019).
Dutta, R. et al. Experimental and theoretical investigation of intracell magnetic coupling-induced variability of spin-transfer torque magnetic RAMs. IEEE Trans. Electron. Devices 70, 5428–5434 (2023).
Carboni, R. et al. Modeling of breakdown-limited endurance in spin-transfer torque magnetic memory under pulsed cycling regime. IEEE Trans. Electron Devices 65, 2470–2478 (2018).
Carboni, R. et al. Understanding cycling endurance in perpendicular spin-transfer torque (p-STT) magnetic memory. In Proc. 2016 IEEE International Electron Devices Meeting 21.6.1–21.6.4 (IEEE, 2017).
Katti, R. R. Magnetoresistive random access memories for space and radiation-hardened applications. In Proc. 2021 IEEE 32nd Magnetic Recording Conference 1–3 (IEEE, 2021).
Jerry, M. et al. Ferroelectric FET analog synapse for acceleration of deep neural network training. In Proc. 2017 IEEE International Electron Devices Meeting 6.2.1–6.2.4 (IEEE, 2018).
Clima, S. et al. Ferroelectric switching in FEFET: physics of the atomic mechanism and switching dynamics in HfZrOx, HfO2 with oxygen vacancies and Si dopants. In Proc. 2020 IEEE International Electron Devices Meeting 4.2.1–4.2.4 (IEEE, 2020).
Yurchuk, E. et al. Charge-trapping phenomena in HfO2-based FeFET-type nonvolatile memories. IEEE Trans. Electron Devices 63, 3501–3507 (2016).
Deng, S. et al. Examination of the interplay between polarization switching and charge trapping in ferroelectric FET. In Proc. 2020 IEEE International Electron Devices Meeting 4.4.1–4.4.4 (IEEE, 2020).
Higashi, Y. et al. Impact of charge trapping and depolarization on data retention using simultaneous P–V and I–V in HfO-based ferroelectric FET. IEEE Trans. Electron Devices 68, 4391–4396 (2021).
Ma, T. P. & Gong, N. Retention and endurance of FeFET memory cells. In Proc. 2019 IEEE 11th International Memory Workshop 1–4 (IEEE, 2019).
Song, Y. et al. Fatigue of ferroelectric field effect transistor: mechanisms and optimization strategies. J. Semicond. 46, 061302 (2025).
Higashi, Y. et al. Impact of charge trapping on imprint and its recovery in HfO2 based FeFET. In Proc. 2019 IEEE International Electron Devices Meeting 15.6.1–15.6.4 (IEEE, 2019).
Crafton, B., Talley, C., Spetalnick, S., Yoon, J. H. & Raychowdhury, A. Characterization and mitigation of IR-drop in RRAM-based compute in-memory. In Proc. 2022 IEEE International Symposium on Circuits and Systems 70–74 (IEEE, 2022).
Lupo, N., Pérez, E., Wenger, C., Maloberti, F. & Bonizzoni, E. Analysis of parasitic effects in filamentary-switching memristive memories using an approximated Verilog — a memristor model. IEEE Trans. Circuits Syst. I Regul. Pap. 66, 1935–1947 (2019).
Lee, Y. et al. Recent progress in memristor array structures and solutions for sneak path current reduction. Adv. Mater. Technol. 10, 2400585 (2025).
Murmann, B. Mixed-signal computing for deep neural network inference. IEEE Trans. Very Large Scale Integr. VLSI Syst. 29, 3–13 (2021).
Zeng, T. et al. Approaching the ideal linearity in epitaxial crystalline-type memristor by controlling filament growth. Adv. Mater. 36, 2401021 (2024).
Islam, R. et al. Improved gradual resistive switching range and 1000 × on/off ratio in HfOx RRAM achieved with a Ge2Sb2Te5 thermal barrier. Appl. Phys. Lett. 121, 082103 (2022).
Wu, W. et al. A methodology to improve linearity of analog RRAM for neuromorphic computing. In Proc. 2018 IEEE Symposium on VLSI Technology 103–104 (IEEE, 2018).
Vishwakarma, K., Datta, A. & Kishore, R. Symmetric linear rise and fall of conductance in a trilayer stack engineered RERAM-based synapse. ACS Appl. Electron. Mater. 2, 3263–3269 (2020).
Kang, J. et al. Cluster-type analogue memristor by engineering redox dynamics for high-performance neuromorphic computing. Nat. Commun. 13, 4040 (2022).
Kempen, T., Waser, R. & Rana, V. 50x endurance improvement in TaOx RRAM by extrinsic doping. In Proc. 2021 IEEE International Memory Workshop 1–4 (IEEE, 2021).
Lee, M. J. et al. A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures. Nat. Mater. 10, 625–630 (2011).
Lee, H. Y. et al. Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM. In Proc. 2008 IEEE International Electron Devices Meeting 1–4 (IEEE, 2008).
Lee, Y. et al. Programmable retention characteristics in MoS2-based atomristors for neuromorphic and reservoir computing systems. ACS Nano 18, 14327–14338 (2024).
Yuan, Y. et al. On-chip atomristors. Mater. Sci. Eng. R Rep. 165, 101006 (2025).
Chang, H.-P., Akinwande, D. & Incorvia, J. A. C. Monolayer hBN RRAM with high DC endurance and low operation voltages using an oxidized top electrode. In Proc. 2024 Device Research Conference 1–2 (IEEE, 2024).
Choi, S. et al. SiGe epitaxial memory for neuromorphic computing with reproducible high performance based on engineered dislocations. Nat. Mater. 17, 335–340 (2018).
Park, J. et al. Multi-level, forming and filament free, bulk switching trilayer RRAM for neuromorphic computing at the edge. Nat. Commun. 15, 3492 (2024).
Kim, S. et al. 4-bit multilevel operation in overshoot suppressed Al2O3/TiOx resistive random-access memory crossbar array. Adv. Intell. Syst. 4, 2100273 (2022).
Ren, K. et al. Controllable SET process in O–Ti–Sb–Te based phase change memory for synaptic application. Appl. Phys. Lett. 112, 073106 (2018).
Zhou, X. et al. Understanding phase-change behaviors of carbon-doped Ge2Sb2Te5 for phase-change memory application. ACS Appl. Mater. Interfaces 6, 14207–14214 (2014).
Khan, A. I. et al. Energy efficient neuro-inspired phase–change memory based on Ge4Sb6Te7 as a novel epitaxial nanocomposite. Adv. Mater. 35, 2300107 (2023).
Bin Hamid, S., Intisar Khan, A., Zhang, H., Davydov, A. V. & Pop, E. Low-energy spiking neural network using Ge4Sb6Te7 phase change memory synapses. IEEE Electron Device Lett. 45, 1819–1822 (2024).
Suri, M. et al. Addition of HfO2 interface layer for improved synaptic performance of phase change memory (PCM) devices. Solid State Electron. 79, 227–232 (2013).
Lin, J. et al. Design of all-phase-change-memory spiking neural network enabled by Ge–Ga–Sb compound. Sci. China Mater. 66, 1551–1558 (2023).
Kim, W. et al. Confined PCM-based analog synaptic devices offering low resistance-drift and 1000 programmable states for deep learning. In Proc. 2019 Symposium on VLSI Technology T66–T67 (IEEE, 2019).
Wu, X. et al. Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory. Nat. Commun. 15, 13 (2024).
Intisar Khan, A. et al. First demonstration of Ge2Sb2Te5-based superlattice phase change memory with low reset current density (−3 MA/cm2) and low resistance drift (−0.002 at 105 °C). In Proc. 2022 IEEE Symposium on VLSI Technology and Circuits 310–311 (IEEE, 2022).
Liu, S. et al. A domain wall-magnetic tunnel junction artificial synapse with notched geometry for accurate and efficient training of deep neural networks. Appl. Phys. Lett. 118, 202405 (2021).
Hissariya, R. & Bhowmik, D. Improving linearity and symmetry of synaptic update characteristics and retentivity of synaptic states of the domain-wall device through addition of edge notches. IEEE Open J. Nanotechnol. 6, 1–9 (2025).
Leonard, T. et al. Shape-dependent multi-weight magnetic artificial synapses for neuromorphic computing. Adv. Electron. Mater. 8, 2200563 (2022).
Ostwal, V., Zand, R., Demara, R. & Appenzeller, J. A novel compound synapse using probabilistic spin-orbit-torque switching for MTJ-based deep neural networks. IEEE J. Explor. Solid State Comput. Devices Circuits 5, 182–187 (2019).
Jeong, J. et al. Spintronic artificial synapses using voltage-controlled multilevel magnetic states. Adv. Electron. Mater. 10, 2300889 (2024).
Raymenants, E. et al. Nanoscale domain wall devices with magnetic tunnel junction read and write. Nat. Electron. 4, 392–398 (2021).
Jeon, J. C., Migliorini, A., Fischer, L., Yoon, J. & Parkin, S. S. P. Dynamic manipulation of chiral domain wall spacing for advanced spintronic memory and logic devices. ACS Nano 18, 14507–14513 (2024).
Zhou, Y. et al. Hybrid-FE-layer FeFET with high linearity and endurance toward on-chip CIM by array demonstration. IEEE Electron Device Lett. 45, 276–279 (2024).
Aabrar, K. A. et al. BEOL-compatible superlattice FeFET analog synapse with improved linearity and symmetry of weight update. IEEE Trans. Electron Devices 69, 2094–2100 (2022).
Yoon, S. J. et al. Improvement in long-term and high-temperature retention stability of ferroelectric field-effect memory transistors with metal-ferroelectric-metal–insulator–semiconductor gate-stacks using Al-doped HfO2 thin films. IEEE Trans. Electron Devices 67, 499–504 (2020).
Ali, T. et al. High Endurance ferroelectric hafnium oxide-based FeFET memory without retention penalty. IEEE Trans. Electron Devices 65, 3769–3774 (2018).
Tan, A. J. et al. Ferroelectric HfO2 memory transistors with high-κ interfacial layer and write endurance exceeding 1010 cycles. IEEE Electron Device Lett. 42, 994–997 (2021).
Zhang, Y. et al. Optimized programming scheme enabling symmetric conductance modulation in HfO resistive random-access memory (RRAM) for neuromorphic systems. IEEE Electron Device Lett. 43, 1203–1206 (2022).
Park, J. et al. TiOx-based RRAM synapse with 64-levels of conductance and symmetric conductance change by adopting a hybrid pulse scheme for neuromorphic computing. IEEE Electron Device Lett. 37, 1559–1562 (2016).
Moon, K., Kwak, M., Park, J., Lee, D. & Hwang, H. Improved conductance linearity and conductance ratio of 1T2R synapse device for neuromorphic systems. IEEE Electron Device Lett. 38, 1023–1026 (2017).
Sakhuja, J., Patil, S., Mondal, S., Lashkare, S. & Ganguly, U. Enhancement in bipolar conductance linearity by one transistor–one resistor (1T1R) cell with non-filamentary PCMO-RRAM as synapse for neural networks. In Proc. 2023 7th IEEE Electron Devices Technology & Manufacturing Conference 1–3 (IEEE, 2023).
Zhou, Z. et al. A new hardware implementation approach of BNNs based on nonlinear 2T2R synaptic cell. In Proc. 2018 IEEE International Electron Devices Meeting 20.7.1–20.7.4 (IEEE, 2018).
Li, C. et al. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks. Nat. Commun. 9, 2385 (2018).
Ninomiya, T. et al. Improvement of data retention during long-term use by suppressing conductive filament expansion in TaOx bipolar-ReRAM. IEEE Electron Device Lett. 34, 762–764 (2013).
Zhang, Y. et al. An improved RRAM-based binarized neural network with high variation-tolerated forward/backward propagation module. IEEE Trans. Electron Devices 67, 469–473 (2020).
Bichler, O. et al. Visual pattern extraction using energy-efficient ‘2-PCM synapse’ neuromorphic architecture. IEEE Trans. Electron Devices 59, 2206–2214 (2012).
Kuzum, D., Jeyasingh, R. G. D., Lee, B. & Wong, H. S. P. Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. Nano Lett. 12, 2179–2186 (2012).
Stern, K. et al. Sub-nanosecond pulses enable partial reset for analog phase change memory. IEEE Electron Device Lett. 42, 1291–1294 (2021).
Shi, Y. et al. Adaptive quantization as a device-algorithm co-design approach to improve the performance of in-memory unsupervised learning with SNNs. IEEE Trans. Electron Devices 66, 1722–1728 (2019).
Joshi, V. et al. Accurate deep neural network inference using computational phase-change memory. Nat. Commun. 11, 2473 (2020).
Taylor, L. & Nitschke, G. Improving deep learning with generic data augmentation. In Proc. 2018 IEEE Symposium Series on Computational Intelligence 1542–1547 (IEEE, 2018).
Zhang, W. & Li, T. Helmet: a resistance drift resilient architecture for multi-level cell phase change memory system. In Proc. 2011 IEEE/IFIP 41st International Conference on Dependable Systems & Networks 197–208 (IEEE, 2018).
Nandakumar, S. R. et al. Experimental demonstration of supervised learning in spiking neural networks with phase-change memory synapses. Sci. Rep. 10, 8080 (2020).
Chen, C. et al. Nonideality suppression and 16-state multilevel cell storage optimization in phase change memory with linear-like circuit. IEEE Trans. Electron Devices 70, 493–498 (2023).
Oh, S. et al. HfZrOx-based ferroelectric synapse device with 32 levels of conductance states for neuromorphic applications. IEEE Electron Device Lett. 38, 732–735 (2017).
Sun, X., Wang, P., Ni, K., Datta, S. & Yu, S. Exploiting hybrid precision for training and inference: a 2T-1FeFET based analog synaptic weight cell. In Proc. 2018 IEEE International Electron Devices Meeting 3.1.1–3.1.4 (IEEE, 2018).
Gong, N. et al. Deep learning acceleration in 14 nm CMOS compatible ReRAM array: device, material and algorithm co-optimization. In Proc. 2022 International Electron Devices Meeting 33.7.1–33.7.4 (IEEE, 2022).
Zhao, G. et al. Design-technology co-optimizations for symmetric linear synapse behaviors in ferroelectric FET based neuromorphic computing. IEEE Trans. Nanotechnol. 21, 747–751 (2022).
Lederer, M. et al. Ferroelectric field effect transistors as a synapse for neuromorphic application. IEEE Trans. Electron Devices 68, 2295–2300 (2021).
Agarwal, S. et al. Achieving ideal accuracies in analog neuromorphic computing using periodic carry. In Proc. 2017 Symposium on VLSI Technology T174–T175 (IEEE, 2017).
Hu, M. et al. Memristor-based analog computation and neural network classification with a dot product engine. Adv. Mater. 30, 1705914 (2018).
Yao, P. et al. Fully hardware-implemented memristor convolutional neural network. Nature 577, 641–646 (2020).
Nandakumar, S. R. et al. Mixed-precision deep learning based on computational memory. Front. Neurosci. 14, 519263 (2020).
Bayat, F. M. et al. Implementation of multilayer perceptron network with highly uniform passive memristive crossbar circuits. Nat. Commun. 9, 2331 (2018).
Yu, S., Kuzum, D. & Wong, H. S. P. Design considerations of synaptic device for neuromorphic computing. In Proc. 2014 IEEE International Symposium on Circuits and Systems 1062–1065 (IEEE, 2014).
Eryilmaz, S. B., Kuzum, D., Yu, S. & Wong, H.-S. P. Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures. In Proc. 2015 IEEE International Electron Devices Meeting 4.1.1–4.1.4 (IEEE, 2015).
Bi, G. Q. & Poo, M. M. Synaptic modifications in cultured hippocampal neurons: dependence on spike timing, synaptic strength, and postsynaptic cell type. J. Neurosci. 18, 10464–10472 (1998).
Fusi, S., Drew, P. J. & Abbott, L. F. Cascade models of synaptically stored memories. Neuron 45, 599–611 (2005).
Branco, T. & Staras, K. The probability of neurotransmitter release: variability and feedback control at single synapses. Nat. Rev. Neurosci. 10, 373–383 (2009).
Laborieux, A., Ernoult, M., Hirtzlin, T. & Querlioz, D. Synaptic metaplasticity in binarized neural networks. Nat. Commun. 12, 2549 (2021).
Zanardi, G., Bettotti, P., Morand, J., Pavesi, L. & Tubiana, L. Metaplasticity and memory in multilevel recurrent feed-forward networks. Phys. Rev. E 110, 054304 (2024).
Kireev, D. et al. Metaplastic and energy-efficient biocompatible graphene artificial synaptic transistors for enhanced accuracy neuromorphic computing. Nat. Commun. 13, 4386 (2022).
Bernard, G. et al. Dynamic control of weight-update linearity in magneto-ionic synapses. Nano Lett. 25, 1443–1450 (2025).
Neal, R. M. Bayesian Learning for Neural Networks (Springer, 1996).
Liu, S. et al. Bayesian neural networks using magnetic tunnel junction-based probabilistic in-memory computing. Front. Nanotechnol. 4, 1021943 (2022).
Shim, Y., Chen, S., Sengupta, A. & Roy, K. Stochastic spin–orbit torque devices as elements for Bayesian inference. Sci. Rep. 7, 14101 (2017).
Harabi, K. E. et al. A memristor-based Bayesian machine. Nat. Electron. 6, 52–63 (2023).
Turck, C. et al. The logarithmic memristor-based Bayesian machine. Commun. Eng. 4, 35 (2025).
Neftci, E. O., Pedroni, B. U., Joshi, S., Al-Shedivat, M. & Cauwenberghs, G. Stochastic synapses enable efficient brain-inspired learning machines. Front. Neurosci. 10, 185771 (2016).
Das, H., Patel, K. P., Febbo, R. D., Schuman, C. D. & Rose, G. S. Leveraging stochasticity in memristive synapses for efficient and reliable neuromorphic systems. npj Unconv. Comput. 2, 3 (2025).
Wang, Z. et al. In situ training of feed-forward and recurrent convolutional memristor networks. Nat. Mach. Intell. 1, 434–442 (2019).
Bhattacharjee, A. & Panda, P. Rethinking non-idealities in memristive crossbars for adversarial robustness in neural networks. Preprint at https://arxiv.org/pdf/2008.11298 (2020).
Liu, Y., Mao, S., Mei, X., Yang, T. & Zhao, X. Sensitivity of adversarial perturbation in fast gradient sign method. In Proc. 2019 IEEE Symposium Series on Computational Intelligence 433–436 (IEEE, 2019).
Deng, Y. & Karam, L. J. Universal adversarial attack via enhanced projected gradient descent. In Proc. 2020 IEEE International Conference on Image Processing 1241–1245 (IEEE, 2020).
Barve, S., Shukla, S., Dinakarrao, S. M. P. & Jha, R. Adversarial attack mitigation approaches using RRAM-neuromorphic architectures. In Proc. ACM Great Lakes Symposium on VLSI 201–206 (Association for Computing Machinery, 2021).
Yamauchi, K. et al. Conductance variation-assisted adversarial attack robustness on 40 nm TaOx-based ReRAM CiM. In Proc. 2025 IEEE International Reliability Physics Symposium 1–6 (IEEE, 2025).
Lin, Y. et al. Demonstration of generative adversarial network by intrinsic random noises of analog RRAM devices. In Proc. 2018 IEEE International Electron Devices Meeting 3.4.1–3.4.4 (IEEE, 2018).
Lammie, C., Büchel, J., Vasilopoulos, A., Le Gallo, M. & Sebastian, A. The inherent adversarial robustness of analog in-memory computing. Nat. Commun. 16, 1756 (2025).
Rajasekharan, D., Rangarajan, N., Patnaik, S., Sinanoglu, O. & Chauhan, Y. S. SCANet: securing the weights with superparamagnetic-MTJ crossbar array networks. IEEE Trans. Neural Netw. Learn. Syst. 34, 5693–5707 (2023).
Koh, D. et al. Closed loop superparamagnetic tunnel junctions for reliable true randomness and generative artificial intelligence. Nano Lett. 25, 3799–3806 (2025).
Berdan, R. et al. Emulating short-term synaptic dynamics with memristive devices. Sci. Rep. 6, 18639 (2016).
Zohora, F. T., Karia, V., Soures, N. & Kudithipudi, D. Probabilistic metaplasticity for continual learning with memristors. Sci. Rep. 14, 29496 (2024).
Lee, J. K., Kwon, O., Jeon, B. & Kim, S. Reservoir computing for temporal data processing using resistive switching memory devices based on ITO treated with O2 plasma. IEEE Trans. Electron Devices 70, 5651–5656 (2023).
Fan, X. et al. Metaplasticity-enabled graphene quantum dot devices for mitigating catastrophic forgetting in artificial neural networks. Adv. Mater. 37, 2411237 (2025).
Park, S. et al. Neuromorphic speech systems using advanced ReRAM-based synapse. In Proc. 2013 IEEE International Electron Devices Meeting 25.6.1–25.6.4 (IEEE, 2013).
Doevenspeck, J. et al. Multi-pillar SOT-MRAM for accurate analog in-memory DNN inference. In Proc. 2021 Symposium on VLSI Technology 1–2 (IEEE, 2021).
Kim, M. K. & Lee, J. S. Ferroelectric analog synaptic transistors. Nano Lett. 19, 2044–2050 (2019).
Wu, W. et al. Improving analog switching in HfOx-based resistive memory with a thermal enhanced layer. IEEE Electron Device Lett. 38, 1019–1022 (2017).
Kumar, A. et al. Filament-free bulk RRAM with high endurance and long retention for neuromorphic few-shot learning on-chip. In Proc. 2024 IEEE International Electron Devices Meeting 1–4 (IEEE, 2024).
Zhou, Y. et al. A compact writing scheme for the reliability challenges in 1T multi-level FeFET array: variation, endurance, and write disturb. IEEE Electron Device Lett. 45, 2387–2390 (2024).
Chen, P. Y., Peng, X. & Yu, S. NeuroSim: a circuit-level macro model for benchmarking neuro-inspired architectures in online learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37, 3067–3080 (2018).
Kim, S., Lim, M., Kim, Y., Kim, H. D. & Choi, S. J. Impact of synaptic device variations on pattern recognition accuracy in a hardware neural network. Sci. Rep. 8, 2638 (2018).