Arm filled in major architectural gaps for its forthcoming AGI data center processor at Hot Chips 2026 this week, detailing a dual-chiplet design built on TSMC’s N3P process that prioritizes memory locality and bandwidth over the heterogeneous compute-and-I/O separation favored by rivals.

The AGI CPU, which Arm has said will begin shipping in late 2026, packs 64, 128, or 136 Neoverse V3 cores running at 2.80 GHz to 3.70 GHz. Each core features a 10-wide frontend and decode, 10-wide dispatch, 8-wide retire, a 384-plus entry out-of-order window, two 128-bit vector engines, and 2MB of L2 cache. The full package offers up to 272 MB of system-level cache.

Each of the two CSS V3 chiplets contains 50 billion transistors and 70 V3 cores, with four cores per chiplet serving as redundancy to improve manufacturing yield. The chiplets connect over a 16×16 UCIe link running at 32 GT/s, delivering 2 TB/s of aggregated die-to-die bandwidth. The processor carries a 300W thermal design power.

Arm’s most notable departure from industry convention is its decision to place compute and I/O on the same die rather than splitting them into separate chiplets. AMD, Intel, and now Nvidia have all embraced heterogeneous designs that separate compute dies from I/O dies hosting memory controllers. Arm argues its approach enables sub-100-nanosecond DRAM latency and 844.8 GB/s of memory bandwidth when paired with DDR5-8800, since memory traffic need not traverse a die-to-die link to reach a controller on another chiplet.

Each chiplet uses an 8×9 CMN-S3 mesh, a low-latency interconnect linking cores, memory, I/O, and accelerators. The mesh incorporates a 128 MB distributed system-level cache, snoop filtering, and hierarchical caching through what Arm calls a Super Home Node, a logic block that acts as a distribution center for on-chip traffic. Arm designed the coherent system to extend beyond the die and socket, conceptually closer to Intel’s distributed Xeon 2D mesh than AMD’s EPYC approach, where compute chiplets connect to a central I/O die.

The memory subsystem is a centerpiece of the design. Two six-channel DDR5 controllers per socket support up to 3 TB per chiplet and 6 TB per socket. The controllers feature fully out-of-order command scheduling, bank-parallelism-optimized address mapping, and programmable page policies to extract more effective bandwidth. Anti-starvation mechanisms help maintain predictable service under heavy load, while Memory Partitioning and Monitoring (MPAM) provides bandwidth limiting and monitoring with QoS-based traffic prioritization. The subsystem also includes Chipkill-class single-DRAM-device failure correction, memory scrubbing, row-hammer mitigation, repair support, error injection, and RAS error logging.

On the I/O side, the AGI CPU offers 96 PCIe 6.0 lanes using the CXL 3.0 protocol for memory expansion, plus four PCIe 4.0 lanes and I3C, I2C, and SPI interfaces.

Arm is positioning the processor primarily for AI servers and agentic AI systems, where memory performance plays an outsized role. The company’s goal, it said, is to maximize bandwidth per core.

What Arm has not provided is conventional benchmark data. There are no SPEC CPU2017 or SPECrate results, no integer or floating-point throughput figures, and no direct socket-to-socket comparisons against current AMD EPYC or Intel Xeon processors in real-world server workloads. The company’s primary performance claim remains an estimated 2X performance per rack versus the latest x86 platforms, a metric that follows Nvidia’s lead in evaluating processors at the rack level rather than through traditional single-socket benchmarks.

The disclosure lands amid an intensifying race for agentic AI data center silicon. At the same symposium, Nvidia detailed its 88-core Vera CPU with spatial multithreading and 1.2 TB/s of SOCAMM2 memory bandwidth, while Intel peeled back layers on its Crescent Island AI accelerator built on the Xe3P architecture. Arm’s AGI enters this field with a distinctly memory-centric pitch, betting that latency-sensitive and agentic workloads will reward its monolithic chiplet philosophy over the modular approaches of its competitors.

With commercial shipments slated for the coming months, the unanswered performance question looms large. Arm says the processor works as planned and remains on track, but until independent benchmarks emerge, customers will have to weigh the architectural arguments on their own merits.