May 28, 2026
Agentic verification is being recognized as a significant shift in how electronic design verification is approached, according to a recent report from Semiengineering.com. The source notes that the transformation is just beginning, with current steps laying the groundwork for larger changes.
For decades, it has been possible to design more than can be fully verified. Verification tools and methodologies have not evolved fast enough to close this gap, and findings from the Siemens/Wilson Research study indicate the situation is worsening.
Advancements in artificial intelligence are prompting questions about whether AI will help close the gap or handle rising complexity, and about its impact on engineering jobs. In the longer term, the tools themselves will need to be assessed for suitability in the age of AI. What is clear is that verification is about to undergo a significant transformation, and being left behind is not an option for EDA or design houses.
Abhi Kolpekwa, senior vice-president and general manager at Siemens EDA, explained that agentic verification is the orchestration of a verification flow by agents, implemented by EDA tools and technologies. He noted that agents will handle repetitive, mechanical tasks such as running an engine, collecting and analyzing data, and recommending next steps.
Ramesh Narayanaswamy, a member of the technical staff at Synopsys, pointed out that past scripts were largely deterministic, whereas agentic solutions use an orchestrator that can reason and adjust its path dynamically based on context.
Paul Graykowski, director of product marketing at Cadence, provided an example: an agent analyzes a UVM error message, explains it, and automatically explores signal relationships, using a chatbot to formulate a response that may even suggest a fix.
Hamid Shojaei, distinguished engineer at Cadence, emphasized that the first step in design verification is understanding the design. If an agent cannot understand the design reliably, the quality of the test plan and test bench will be low.
Dave Kelf, CEO of Breker Verification Systems, noted that AI can help engineers understand complex specifications such as RISC-V. He said that AI can read a spec, generate a verification plan, and produce a high-level graph, which tools can then use to generate tests, especially in system verification.
Graykowski added that a coverage tool will need to build a mental model from inputs such as test code, RTL, and specs. Based on that model, it can generate test plans, coverage points, and UVM code, providing a different approach to verification automation.
Kelf explained that when a failure occurs, AI must back-annotate to the spec and verification plan to identify discrepancies, which AI is particularly good at.
Shojaei noted that when RTL is updated, AI can understand changes, tell which tests need updating, run the tool, get feedback, and debug. He stressed the need for key analysis tools to help AI understand changes and reason correctly, otherwise large language models may hallucinate.
Shelly Henry, founder and CEO of Moores Lab AI, said that if AI creates a model from a specification without context from files like FSDB and log files, it may make mistakes. Once it has that context, it can analyze everything and suggest fixes if the original intent was not captured correctly.
Alexander Petr, senior director at Keysight EDA, highlighted limitations in analog verification. Foundational models for digital RTL are trained on widely available internet data, but analog IP such as ball filters or power amplifiers is not publicly available. Analog problems are also multi-domain and multi-physics, making them harder to fix.
William Wang, CEO of ChipAgents, stated that the real gains of agentic verification are already clear: it automates low-leverage, time-consuming work such as writing test vectors, setting up UVM testbenches, triaging failures, and debugging, allowing engineers to focus on architecture and corner-case reasoning.
Stefan Birman, partner at AMIQ Consulting, noted that the value of AI assistants in guiding tool usage is evident, but users are concerned about accuracy, the non-deterministic nature of AI, and the unpredictability of costs.
Henry described a case where she verified an AXI-to-APB bridge using an AI platform, writing all test cases without writing a single line of code. She created a complete test bench with monitors, drivers, scoreboards, and a reference model, found and fixed bugs, and closed coverage in under 48 hours, whereas the traditional method would take two months.
Petr observed that for analog, a solution will be slower and less effective initially, and only after many uses does it become better than a human. He noted that the digital side does not face this sales problem because digital solutions work well from the start.
Narayanaswamy addressed concerns about AI token costs, saying that budgets are necessary to prevent AI from running forever. He noted that if an engineer’s loaded cost is $300k or $400k, consuming $2k in tokens is a fraction of that cost and likely worthwhile, though it can be a budget surprise.
Kolpekwa said that budgets will need to account for GPU cycles, and headwinds will be non-human, involving budget and cost. He mentioned legalities around IP exposure and LLM reliability, as well as computational cost, but expressed hope that agentic verification will reduce complexity and improve total cost of ownership.
Andy Nightinghale, vice president of product management and marketing at Arteris, emphasized that the value proposition must be carefully measured. The strongest business case comes when agents reduce engineering iteration by shortening debug cycles, improving coverage closure, and identifying integration issues earlier. The key metric is whether verification teams reach signoff confidence faster with fewer silicon escapes.
Wang reiterated that while AI infrastructure has a cost, the ROI is overwhelmingly positive in the semiconductor context, citing that a single day of tapeout delay can translate into billions in opportunity cost for companies like Nvidia.
Graykowski noted that agentic verification is not a one-size-fits-all solution. Some tasks are quicker when done manually, while an LLM can work wonders for others. Asking a question with the context of an entire SoC may take hours, and context memory limits pose further challenges.
Shojaei advised that engineers need to remain in the driving seat. If a customer finds one out of one hundred assertions generated by AI is wrong, the engineer must review results step by step. Relying solely on the agent is risky, and chip designers should not trust AI 100% at this point.