Samsung Electronics has formalized its 1.4-nanometer (nm) process roadmap targeting mass production in 2029, while aggressively emphasizing the strengthening of its foundry collaboration with Nvidia. At the ‘SAFE Forum 2026’ held at its Seocho office in Seoul on July 1, the company unveiled its next-generation advanced process technologies and AI semiconductor ecosystem strategy, signaling its intent to seize leadership in the global foundry market.
The centerpiece of the event was a ‘Grok 3 Language Processing Unit (LPU)’ wafer personally signed by Nvidia CEO Jensen Huang. Samsung displayed the physical wafer at the most prominent location near the venue entrance, underscoring its partnership with Nvidia. Attendees from client and partner companies showed intense interest, peppering staff with questions such as “Which Samsung technology was applied?” and “Is this currently in mass production?”
Grok 3 is an AI inference chip developed by Grok, a startup acquired by Nvidia last year, and is currently being manufactured by Samsung using its 4nm process. Jun Young-hyun, Vice Chairman of Samsung Electronics, stated after a private meeting with CEO Jensen Huang on the 8th of last month, “We are collaborating with Nvidia on autonomous driving chips and Grok chips using 4nm and 8nm processes, and we are also discussing next-generation collaboration.” This is interpreted as a strong signal that Samsung is likely to secure Nvidia orders for cutting-edge processes, including the upcoming 2nm node.
In his keynote speech, Shin Jong-shin, Head of the Design Platform Development Office at Samsung’s Foundry Business, stated, “We will accelerate collaboration with global AI and high-performance computing (HPC) customers and strengthen our role as a platform for South Korea’s domestic system semiconductor industry.” Regarding the highly anticipated 1.4nm process (SF1.4), he provided a specific timeline: “Development is progressing smoothly with a target for mass production in 2029, and an enhanced node, SF1.4 Plus, featuring improved yield and performance, is scheduled for introduction in 2030.”
The 2nm process roadmap is also evolving in phases. Samsung plans to apply the performance-enhanced SF2P Plus version between 2027 and 2028, before expanding to the next-generation SF2X process, which maintains compatibility with existing design IP assets. Shin emphasized that process development for AI memory is proceeding in parallel, noting, “We are actively developing 3D DRAM files for HBM4E, HBM5, and HBM5E on the 2nm process.”
The importance of Design-Technology Co-Optimization (DTCO) for overcoming the physical limitations of process miniaturization was also highlighted. “For the 2nm process, we reduced power consumption by 26%, and more than half of that improvement came from DTCO,” Shin explained, forecasting that “as generations advance, DTCO will account for almost all performance improvements.” He also noted that Samsung has secured high-density data storage capabilities by implementing SRAM—an essential component for AI chips—in the world’s smallest form factor.
Samsung also detailed its strategy for integrating logic chips and memory. The company is manufacturing the base die for HBM4, the sixth-generation high-bandwidth memory, on its proprietary 4nm process (SF4X) and has secured technical margin to stably boost speeds up to 11.7 gigabits per second (Gbps). Notably, Samsung plans to drastically reduce customer design and simulation time by converting chip-to-chip connection verification into a digital automated method called 3D ‘DRAM Pie.’
The forum featured booths from 21 partner companies across electronic design automation (EDA), design IP, design solutions, and advanced packaging. Park Sung-hyun, CEO of AI fabless company Rebellions, announced, “We developed the ‘Rebel100’ NPU based on Samsung’s 4nm foundry process and advanced packaging,” adding, “We will collaborate in the AI semiconductor space to build sovereign AI.” Jean-Marie Brunet, Senior Vice President at Siemens EDA, introduced design verification and packaging support solutions for 2.5D and 3D heterogeneous chip integration.
Han Jin-man, President and head of Samsung Foundry, was scheduled to host a dinner that evening with C-level executives from major client and partner companies to discuss strategies and solutions for turning the foundry business profitable. With the world’s top foundry, TSMC, facing supply disruptions amid an explosion in AI semiconductor orders, Samsung is gaining attention as an alternative, leveraging its comprehensive semiconductor capabilities to offer HBM, foundry services, and advanced packaging together.
To enhance communication with customers and partners, Samsung will completely overhaul its B2B website ‘Connect’ starting in 2026. The revamp will feature an intuitive user interface and experience (UI/UX) and introduce new AI chatbot capabilities for real-time responses and document search functions. Approximately 400 client and partner company representatives attended the event, demonstrating strong interest in Samsung’s foundry ecosystem strategy for leading the AI semiconductor era.