{"id":13568,"date":"2026-04-23T05:05:36","date_gmt":"2026-04-23T05:05:36","guid":{"rendered":"https:\/\/www.europesays.com\/ai\/13568\/"},"modified":"2026-04-23T05:05:36","modified_gmt":"2026-04-23T05:05:36","slug":"how-agentic-ai-chip-design-built-a-full-risc-v-core","status":"publish","type":"post","link":"https:\/\/www.europesays.com\/ai\/13568\/","title":{"rendered":"How Agentic AI Chip Design Built a Full RISC-V Core"},"content":{"rendered":"

In 2020, researchers fine-tuned a GPT-2 model to design fragments of logic circuits<\/a>; in 2023, researchers used GPT-4<\/a> to help design an 8-bit processor<\/a> with a novel instruction set; by 2024, a variety of LLMs could design and test chips<\/a> with basic functionality, like dice rolls (though often these were flawed).<\/p>\n

Now Verkor.io, an AI chip design<\/a> startup, claims a bigger milestone: a RISC-V <\/a>CPU core designed entirely by an agentic AI system. The CPU, dubbed VerCore, has a clock speed of 1.5 gigahertz and performance similar to a 2011-era laptop CPU. <\/p>\n

Suresh Krishna<\/a>, cofounder at Verkor.io<\/a>, says the team\u2019s key claim is that this approach is more effective than using only specialized AI systems for specialized tasks within the overall design process. \u201c What we learned is that the better approach is to let the AI agent solve the whole problem,\u201d he says.<\/p>\n

Bringing Human Workflows to Agentic AI<\/p>\n

Verkor.io\u2019s agentic system is called Design Conductor<\/a>, and it\u2019s not itself an AI model. It\u2019s a harness for large language models<\/a> (LLMs). A harness is software that forces an AI agent to proceed through structured steps. In this case, the steps are like those a team of human chip architects would follow: design, implementation, testing, and so on. The harness also manages subagents and a database of related files.<\/p>\n

That means it can work autonomously with only an initial prompt\u2014in this case a 219-word design specification\u2014from the user. (The prompt is published in the Design Conductor paper<\/a>.) It outputs a Graphic Design System II (GDSII) file<\/a>, which can be used in existing electronic design automation<\/a> (EDA) software.<\/p>\n

Synopsys<\/a> and Cadence<\/a>, two major players in EDA software, also have agentic AI tools. These allow chip architects to automate some tasks with AI agents<\/a>. Design Conductor is different because it\u2019s built to handle chip design<\/a> from spec to completion with full autonomy, something major EDA companies have not yet touted.<\/p>\n

Ravi Krishna<\/a>, founding engineer at Verkor.io, says Design Conductor\u2019s workflow is \u201cmirrored after the traditional process a human engineer might use.\u201d It analyzes the specification, then writes and debugs a register-transfer level, or RTL, file (an abstraction of the CPU\u2019s data flow) before iterating through subtasks like power delivery, signal timings, and layout, which are again checked against the specification. Some tasks, like layout, call tools<\/a> to assist the agent. \u201cIt\u2019s an iterative system.\u201d<\/p>\n

The system took 12 hours to create the VerCore design. That\u2019s not long, but, because it uses AI agents, you might imagine it taking more or less time based on the number of agents thrown at it. However, Ravi Krishna says it\u2019s not that simple, because some design tasks aren\u2019t easily parallelized. <\/p>\n

However, the general improvement of AI models<\/a> over time has proven essential. \u201cI remember that around the middle of last year, we tried to build a floating-point multiplier with the models of that time. It was slightly beyond what they could do,\u201d says Ravi Krishna. VerCore\u2014designed in December 2025\u2014 represents an increase in capability since then. \u201cIf it can\u2019t do it today, it\u2019ll do it in six months,\u201d he says. \u201cI don\u2019t know if that\u2019s a scary thing or a good thing.\u201d<\/p>\n

A First for AI Chip Design<\/p>\n

VerCore uses the RISC-V<\/a> instruction set architecture (ISA), a popular open-standard ISA that\u2019s beginning to break out of niche applications, like storage controllers, into systems on a chip (SoCs) that can power laptops or smartphones<\/a>. The CPU\u2019s exact clock speed is 1.48 GHz and it achieved a score of 3,261 on the CoreMark<\/a> processor core benchmark. <\/p>\n

Verkor says this puts VerCore\u2019s performance in line with the CPU core performance of Intel\u2019s Celeron SU2300<\/a>. Whether that sounds impressive depends on your perspective. The Celeron SU2300, which arrived in 2011, uses Intel\u2019s Penryn CPU architecture<\/a>, which debuted in November of 2007.<\/p>\n

In other words, VerCore is no threat to leading-edge CPUs, but it\u2019s notable for two reasons.<\/p>\n

VerCore is the first RISC-V CPU core designed by an AI agent. Previous examples of AI chip design presented portions of a design but didn\u2019t present a complete core. Ravi Krishna says the company wanted to target a design that an AI agent hadn\u2019t previously accomplished. \u201cFrom the perspective of trying to push the limits of what AI models can do, that was interesting to us,\u201d he says.<\/p>\n

And while VerCore\u2019s theoretical performance has limits, it\u2019s enough to suggest the design could be useful. Indeed, RISC-V is popular because it provides an ISA that\u2019s free to use (RISC-V is an open standard). RISC-V chips generally aren\u2019t as quick as their x86 and Arm peers, but they\u2019re less expensive. <\/p>\n

There\u2019s one final caveat worth mentioning; the chip has not been physically produced. VerCore was verified in simulation with Spike<\/a>, the reference RISC-V ISA simulator, and laid out using the open-source ASAP7 PDK<\/a>, an academic design kit that simulates a 7-nanometer production node. Both tools are commonly used for RISC-V design. VerCore says its CPU can run a variant of uCLinux<\/a> in simulation. <\/p>\n

Skeptics will have a chance to judge for themselves. Verkor.io plans to release design files at the end of April. This will include the VerCore CPU and several other designs recently completed by the AI agent system. Verkor also plans to show an FPGA<\/a> implementation of VerCore at DAC<\/a>, the leading electronic design<\/a> automation<\/a> conference.<\/p>\n

Should Chip Designers Worry about AI Agents Taking Their Jobs?<\/p>\n

An AI chip designer that can bang out a CPU in 12 hours might seem like troubling news for flesh-and-blood engineers, but Design Conductor has its limitations. The team at Verkor.io say that despite improvements, LLMs still lack the intuition a human can bring.<\/p>\n

Design Conductor can fall down rabbit holes that a human engineer would avoid. In one instance the agent made a mistake in timing, meaning that data was not moved across the CPU in agreement with its clock cycle. The model didn\u2019t recognize the cause and made broad changes while hunting for the fix. It did eventually find a fix, but only after reaching many dead ends. \u201cBasically, we are trading off experience for compute,\u201d says David Chin<\/a>, vice president of engineering at the startup.<\/p>\n

Suresh Krishna concurs and adds that Design Conductor\u2019s brute-force approach is likely to become less efficient as agentic systems tackle more complex designs. \u201cIt\u2019s a nonlinear design space, so the compute grows very quickly,\u201d he says. \u201cAs a practical matter, expert guidance and common sense helps a lot.\u201d<\/p>\n

Despite such issues, agentic systems like Design Conductor might accelerate chip design by accelerating iteration. They may also make design accessible to small teams that otherwise lack the resources or head count to pull off a project.<\/p>\n

\u201cIt\u2019s not at the point where you can have one person. I would say you still need five to ten, all experts in different areas,\u201d says Ravi Krishna. \u201cThat team could get you to [a production-ready chip design] at this point.\u201d<\/p>\n

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