It was also a year in which EDA veterans started talking seriously about unconventional compute and quantum computing as part of the longer\u2011term path to keep engineering progress from stalling under its own power and complexity demands.<\/p>\n
Before we dive into EE Times\u2019 interviews with executives on the show floor, a quick comment on the temporary new venue for DAC 2026, the chips to systems conference<\/a>. Long Beach, California, seemed like an unusual venue given that DAC had been held in San Francisco in recent years, close to where many attendees are based. However, as many EDA veterans will recall, DAC moved around in the past, including to Anaheim, New Orleans, Orlando, and Las Vegas. The location was not a deterrent then, as those who wanted to attend did attend, and this year was no different. Next year, DAC moves to San Jose, California.<\/p>\n Sections in this article:<\/p>\n \t\t\t\t\t By \u00a0Juergen Jaeger,\u00a0Director of Prototyping Product Strategy,\u00a0Siemens EDA\u00a0\u00a0 08.10.2026<\/p>\n \t\t\t\t\t By Piyush Sancheti, VP Central Engineering Solutions (3D IC), and Todd Burkholder, 3D IC Technology Writer, Siemens EDA\u00a0 08.05.2026<\/p>\n \t\t\t\t\t By Alessandro Chimera, Industry Solutions Lead, Spotfire\u00a0 08.05.2026<\/p>\n Nvidia\u2019s debut at DAC: engineers elevated to system-level rather than tool-level<\/p>\n Focusing on physics models and analog design<\/p>\n Wally Rhines reflects on one year at Silvaco and agentic AI in EDA<\/p>\n Intel on advanced packaging and the need for STCO<\/p>\n Synopsys panel: open EDA systems and business models based on token usage<\/p>\n Standards: Accellera on functional safety and Intel on PADKs<\/p>\n A new class of agentic AI startups designing agents<\/p>\n Achieving quantum compute at scale: the path to wafer-scale integration<\/p>\n EDA is cool again<\/p>\n Nvidia\u2019s debut at DAC: engineers elevated to system-level rather than tool-level<\/p>\n The agentic engineering theme has been bandied around so much in the last 18 months, and this year is no exception. Tim Costa, Nvidia\u2019s VP and GM for industrial engineering and quantum, marked Nvidia\u2019s first appearance at DAC\u2014no doubt convinced that Nvidia needed to support the EDA industry, even if only through speaking engagements, as part of the broader narrative around developing next-generation chips. Costa and other executives drummed home a message that Nvidia loves to tell: a world in which the limit on product development is no longer how many experts you can hire, but how much compute you can throw at a chain of tools orchestrated by long\u2011running AI agents.<\/p>\n Ravi Subramaniam, chief product management officer at Synopsys, said, \u201cThere\u2019s $1.4 trillion spent on engineering. About 10% is digital, 90% is physical. We\u2019re moving toward taking that 90% onto computers.\u201d He said that while Synopsys had been working on the AI aspects since 2017, things have changed dramatically with respect to agentic AI. \u201cAt first, it was really driven by chat interactions, small, very short runtime. But now, as the models have evolved, and you can handle much longer running workloads, workflows, it gives the opportunity to start really bringing agents and autonomy together, and that\u2019s what we announced here, which is safe, open, long-running autonomous agents for digital verification.\u201d<\/p>\n These agents Subramaniam described sit on top of existing flows: They run verification, thermal analysis, or implementation tools, interpret log files, decide what to try next, and maintain context over days long runs.<\/p>\n Nvidia\u2019s Costa said this is ultimately about supporting engineers in doing what they wanted to do when they entered engineering: \u201cIt is a really exciting time in my mind for the engineers, because instead of being focused on how do I use this one tool, they get to elevate themselves and do what probably brought them into the industry in the first place.\u201d Illustrating this point, he said, \u201cIf you\u2019re in [for example] motorsports, you probably have a passion for speed, aerodynamics, but not for how to use one tool in that workflow, and so engineers will elevate to be system-level thinkers, focused on their mission rather than the task of going to specific tools.\u201d<\/p>\n Synopsys\u2019s Subramaniam added that the industry has reached a point where autonomous, Level 4\u2011style workflow agents (borrowing the automotive industry\u2019s autonomous driving analogy) are moving from demos to early deployments.<\/p>\n Focusing on physics models and analog design<\/p>\n It\u2019s not all about agents, as physics is also a fundamental part of the story. Agentic workflows<\/a> are only as good as the tools and models they orchestrate, bringing the discussion to everything from thermal analysis to advanced packaging.<\/p>\n Startups such as Vinci are targeting thermal and thermomechanical signoff by training physics foundation models that can replace weeks\u2011long simulations with automated analysis behind the firewall. \u201cWe are the ChatGPT of physics\u2014but deployed in production, behind the firewall, not as a hobby,\u201d said Vinci co-founder and CEO Hardik Kabaria, claiming a speedup of about three orders of magnitude over incumbent flows on real semiconductor packages.<\/p>\n \u201cFor a $4 trillion hardware economy, there are only about a million engineers who can really do physics,\u201d he added. \u201cPhysics isn\u2019t going away\u2014we want to enable physics intelligence for everyone, everywhere.\u201d<\/p>\n On the analog design side, Indian startup Maieutic Semiconductors, which has raised $6 million in funding, is trying to do something similar for analog design knowledge. The company uses what co-founder Ashish Lachhwani calls a \u201cSocratic\u201d AI that questions engineers and mines internal data to surface the tacit, tribal know\u2011how embedded in senior designers, particularly around analog expertise. Lachhwani, previously a co-founder of Steradian Semiconductors, which was acquired<\/a> by Renesas Electronics in 2022, said, \u201cDigital has had automation and shared data for years. In analog, even a five\u2011transistor circuit can take years to perfect. It\u2019s not about just searching. It\u2019s about knowing what it is and figuring out what to do next\u2014that\u2019s where our added intelligence comes in.\u201d<\/p>\n Wally Rhines reflects on one year at Silvaco and agentic AI in EDA<\/p>\n In a video interview with EE Times, Silvaco CEO and industry veteran Wally Rhines reflected on his first year at the helm of Silvaco. He highlighted how the arrival of agentic workflows is reshaping technology computer-aided design (TCAD), moving the discipline from a specialized, isolated function toward an automated, accessible core layer for the broader engineering ecosystem.<\/p>\n You can watch the video interview below:<\/p>\n He said the real revolution comes with AI: \u201cAll of a sudden, the world now has processes that are too complex to develop by running pilot wafers. Now we have to develop virtually, and to do that you need synthetic data to build models. Where does that come from? It comes from physics solvers\u2014for Silvaco, that\u2019s 40 years of building up that capability.\u201d<\/p>\n Rhines said he sees agentic AI as a democratizing force across the foundry-to-design interface. Rather than forcing fab engineers or system architects to become TCAD specialists, autonomous agents can query underlying digital twins via natural language, conduct large-scale design of experiments virtually to diagnose yield anomalies, and optimize process steps in real time.<\/p>\n \u201cAgents are the great equalizers,\u201d Rhines said. \u201cThey go look for the best solution. They collect the best data. If I had to be a TCAD expert as a fab engineer, I had to go to the TCAD group. Now I\u2019ve got an agent with an English-language interface that can look it up for me.\u201d<\/p>\n Beyond physics simulation<\/a>, Rhines pointed to custom semiconductor IP as the second critical leg of Silvaco\u2019s growth story\u2014underscored by its acquisition of Mixel in 2025. As systems engineers demand tailored, low-power interface IP, such as MIPI for AR\/VR and automotive sensors, rather than standard off-the-shelf blocks, Silvaco combines zero-defect physical-layer IP with deep, GPU-accelerated TCAD digital twins. Rhines said this gives designers a direct pipeline from atomic-level silicon modeling to full-system realization.<\/p>\n Intel on advanced packaging and the need for STCO<\/p>\n Lalitha Immaneni, VP of semiconductor R&D in the Assembly Test Technology Development organization for Intel, offered a \u2018blunt\u2019 assessment: Design teams are still too often \u201cjumping blindly\u201d into complex stacks without adequate multi\u2011physics guidance or standardized data.<\/p>\n Immaneni cited instances where customer designs with poor copper-density data can force a foundry\u2019s mechanical team to spend three to four weeks cleaning up the database before conducting a three\u2011to\u2011four\u2011week analysis. \u201cThat\u2019s not acceptable at this complexity,\u201d she said.<\/p>\n As the executive responsible for the vision and execution of Intel\u2019s centralized package and board flows and tools, as well as EDA ecosystem readiness for Intel\u2019s packaging and board design needs, Immaneni has a broad perspective on the semiconductor packaging industry.<\/p>\n Intel\u2019s answer is system\u2011technology co\u2011optimization (STCO), built on its package assembly design kits (PADKs)\u2014the packaging equivalent of a PDK (see Intel bolsters EMIB packaging with EDA tools enablement<\/a>). PADKs bundle design rules, reference flows, training materials, and Intel\u2011specific verification scripts for technologies such as EMIB, TSV, and embedded MIM capacitors, co\u2011certified with HBM memory and IP vendors. \u201cVerification is too late,\u201d she argued. \u201cWe should be validating and modeling from the beginning, not discovering warpage after the fact.\u201d<\/p>\n Synopsys panel: open EDA systems and business models based on token usage<\/p>\n A broader silicon-to-systems panel hosted by Synopsys brought together panelists from Synopsys, Qualcomm, and Nvidia. The discussion was chaired and moderated by Prith Banerjee, senior VP of innovation at Synopsys. If you\u2019ve never heard Banerjee speak, he has an authoritative yet humble, professorial style that can politely challenge the status quo. He did just that with two key points on this panel: one related to openness in the EDA ecosystem and the other to the need for EDA business models to change as the industry moves toward agentic AI.<\/p>\n On the first point, Banerjee asked panelists, \u201cIn a world where you will have tools from different vendors, do you see in this world an open, agentic framework or not?\u201d<\/p>\n As a user, Paul Penzes, VP of engineering, probably gave the most illustrative response on where the industry stands. Penzes said, \u201cThe way I see it is that there are three pillars to the equation. First are the fundamental tools [that the EDA tools vendors] provide. There are the LLMs that other companies provide, and then there is the middle layer where it\u2019s the know-how of engineering tools within companies. With a closed system, you would need all three components at a very high level of expertise, which is actually almost impossible.\u201d<\/p>\n He went on to explain that engineers need to experiment with different tools from different vendors depending on which works best for specific parameters to get to their end goal of pushing PPA (power, performance, and area). He said, \u201cFrom our user perspective, you can have an agent end to end, but if you have to push PPA, we have to push tools to the very edge. Sometimes we have to take another tool because on that block, the other tool happens to work better. It\u2019s not because there is anything bad.\u201d<\/p>\n Based on this, Penzes said, \u201cWe can\u2019t afford a closed system because we will not be able to succeed, especially since the mobile market is extremely competitive. Every millimeter matters, and we need an open system where we can actually do some of those sorts of experiments to get the best chip out there.\u201d<\/p>\n On the evolution of the business model, Banerjee commented, \u201cIn this new world of agentic AI, we are actually exploring new business models. The old way of EDA was you buy a piece of software, [with a] perpetual license. Then we move toward lease licenses or timeless licenses. You buy [say] a fusion compiler for $100,000. It\u2019s there for you for a year until you renew it. But in the new world of agentic AI, if these agentic workflows are based on token consumption, the traditional way of \u2018you just get an agentic workflow for $100,000\u2019 will not work because depending on your use at your site, you will burn through so many tokens that we\u2019ll have to pay for that, and that is not fair.\u201d<\/p>\n Banerjee continued, \u201cThe business model has to go toward a consumption-based model. We are still in early days, and we have not clearly articulated the business model, but [I think] that\u2019s kind of the trajectory.\u201d<\/p>\n Standards: Accellera on functional safety and Intel on PADKs<\/p>\n One of the great things about the semiconductor industry is that it moves full speed ahead with innovation, and startups can get funded to the hilt to go and commercialize their innovative technologies. But without standards, scaling and mass deployment can often be a challenge.<\/p>\n EE Times had two conversations on the standards debate\u2014one with Intel on packaging flows and another with the Accellera Systems Initiative\u2014highlighting how much the next wave of automation depends on machine\u2011readable, interoperable specifications.<\/p>\n In a conversation with EE Times, Lu Dai, chairman of the Accellera board, discussed the organization\u2019s role as a standards body that can move quickly while still targeting global impact. One focus area is the draft Functional Safety Language (FSL) 1.0 standard, designed to sit under high\u2011level standards such as ISO 26262.<\/p>\n FSL defines the syntax and semantics of a language and data model for representing and exchanging functional safety intent\u2014focusing on FMEDA (failure modes, effects, and diagnostic analysis)\u2014between tools, teams, and operations across the supply chain, from IP to system level. According to Accellera, by enabling automation, interoperability, and traceability, FSL streamlines the implementation of industry standards such as ISO 26262 and IEC 61508 for safety-critical systems and significantly increases confidence in overall safety compliance.<\/p>\n Dai told EE Times, \u201cISO 26262 is like a government guideline: \u2018You need DFT coverage.\u2019 It doesn\u2019t tell you 80%, 99%, or on which block. [With the proposed FSL standard,] we don\u2019t prescribe 99% coverage. We give you a hook so, if asked, you can say: Here is my requirement, and here is the coverage I actually achieved.\u201d<\/p>\n FSL is expressed as metadata\u2014similar in spirit to unified power format (UPF) and other power formats\u2014so tools can parse and reason about safety requirements and coverage hooks directly. In the background, Accellera is already thinking about how pieces such as FSL, portable stimulus, and mixed\u2011signal interface standards ultimately feed into the IEEE and possibly ISO ecosystems.<\/p>\n For Intel, PADKs play a similar role at the packaging level, encoding not just rules but system\u2011level co\u2011optimization guidelines. This allows customers to mix tools from Cadence, Synopsys, and Siemens without losing the link to Intel\u2019s certified flows. That interoperability, in turn, is essential for any realistic agentic workflow that crosses foundries, IP providers, and tool vendors.<\/p>\n A new class of agentic AI startups designing agents<\/p>\n As EE Times reported in ChipAgents CEO on Latest Funding for Agentic AI in EDA<\/a>, a new class of startups has emerged over the last year or so, built on the idea that the primary design artifact of the future will be agents, rather than RTL.<\/p>\n One such company, founded and led by the former head of Nvidia\u2019s design automation research Mark Ren, suggested we should now be talking about ADA, or agentic design automation, as a new stack that runs in parallel to, and eventually becomes intertwined with, classical EDA.<\/p>\n Ren, founder and CEO of Agentrys, said, \u201cAgentic EDA sounds like a wrapper. We\u2019re talking about rethinking the whole design automation stack\u2014designers won\u2019t design chips; they\u2019ll design agents.\u201d He questioned the value of companies such as design houses relying solely on third\u2011party agents: \u201cIf they only use external agents, what do they really own? The special sauce needs to be their own agents.\u201d<\/p>\n Agentrys\u2019s platform is built in three layers: a secure integration layer that touches every tool and script; a self\u2011improvement layer that lets agents iteratively refine themselves; and \u201cagent\u2011native tools\u201d designed for fast, interactive debug and reasoning rather than overnight batch runs. The business model combines on\u2011premise software with runtime\u2011metered agent licenses.<\/p>\n A different approach comes from Normal Computing, which pairs EDA tools with \u2018unconventional\u2019 compute hardware such as analog matrix engines and stochastic chips. The company is funded in part by ARIA<\/a>, the U.K. government\u2019s Advanced Research and Invention Agency, often compared with the U.S. Defense Advanced Research Projects Agency (DARPA). \u201cWe don\u2019t need to push performance at all costs; our goal is two orders of magnitude efficiency improvement,\u201d said Peter Vigil, DV lead at Normal Computing. He argued that leaning into noise through stochastic computing could help avoid building a new hyperscale data center every time a model grows.<\/p>\n Achieving quantum compute at scale: the path to wafer-scale integration<\/p>\n In the opening keynote at DAC 2026, we heard from John Martinis, a distinguished physicist, 2025 Nobel laureate in physics, and CTO and co-founder of Qolab. His talk provided a glimpse of what might come next for quantum computing.<\/p>\n Martinis walked through the progression from early superconducting tunnel junction experiments\u2014designed to show that a macroscopic electrical circuit could behave as a quantum system\u2014through Google\u2019s 2019 quantum supremacy experiment. The experiment\u2019s cross\u2011entropy benchmarking fidelity matched error predictions and suggested there was \u201cno hidden physics\u201d blocking the scaleup of quantum.<\/p>\n Looking ahead, Martinis argued that the current \u201cgold chandelier\u201d machines\u2014massive cryogenic stacks with thousands of wires feeding a single chip\u2014have to give way to wafer\u2011scale integration that looks much more like a modern semiconductor fab flow. \u201cWe want to bring the cost of a general\u2011purpose quantum computer down from tens of billions to about what a regular supercomputer costs,\u201d he said.<\/p>\n EDA is cool again<\/p>\n If there was one theme that summed up where the industry is heading, it came from John Lee, senior VP of EDA software and hardware product management at Synopsys. In the Synopsys executive panel discussion with Nvidia and Qualcomm, he stated that the industry had made EDA \u201ccool again\u201d. That sentiment was palpable, on the show floor, among conference attendees.<\/p>\n Lee commented, \u201cI said the industry is cool again. The stakes are so high. The smartest people will be attracted to this industry to help, not to solve the agentic stuff we\u2019re talking about, but also the fundamentals of what drives that. I\u2019m optimistic, and being here at DAC, it\u2019s great to see the startups out here. And on the hardware side, I think there\u2019s going to be a tremendous opportunity, incentive, and innovation to drive that.\u201d<\/p>\n Synopsys\u2019s Subramaniam added, \u201cEssentially, we now have the most comprehensive set of long-running autonomous workflows. And the autonomous piece is really the next piece from the system. Automated, assistive, and now autonomous. We\u2019re at the very beginning of the beginning. We know we\u2019re on the technology hype cycle, and agents are at the peak right now, and so the novelty is there. [The] novelty effect is very high. [The] value effect is what\u2019s got to get proven, and so we expect customers are going to build their own agents.\u201d<\/p>\n The DAC 2026 exhibition and conference certainly felt like it had a buzz around it. The new temporary venue, combined with a raft of new AI agent EDA companies, reflected an industry looking for ways to navigate the complexity of advanced chip designs, advanced packaging, and multiple tools. It\u2019s a whole new world for EDA.<\/p>\n Read also:<\/p>\n DAC 2025: Agentic AI In EDA Is Just Getting Started, And Chiplets Are All The Rage<\/a><\/p>\n DAC 2025: Towards Multi-Agent Systems In EDA<\/a><\/p>\n DAC 2024 Day 3: Wafer-Level Digital Twins, Reusable Chiplets<\/a><\/p>\n DAC 2024 Day 2: Wider Context For Systems Design, Plus GenAI EDA Startups<\/a><\/p>\n DAC 2024 Day 1: Designing Chiplets and AI with RISC-V<\/a><\/p>\n AGENTIC AI<\/a>, AI AND BIG DATA<\/a>, CHIP DESIGN<\/a>, MULTI-PHYSICS<\/a>, QUANTUM COMPUTING<\/a>\n <\/p>\n MAIEUTIC SEMICONDUCTORS<\/a>, NVIDIA<\/a>, SILVACO<\/a>, SYNOPSYS<\/a>\n <\/p>\n","protected":false},"excerpt":{"rendered":"\/\/php echo do_shortcode(‘[responsivevoice_button voice=”US English Male” buttontext=”Listen to Post”]’) ?> If DAC 2025 was about agentic AI arriving…\n","protected":false},"author":2,"featured_media":136516,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[179,7493,35898,3139,67620,2844],"class_list":["post-136515","post","type-post","status-publish","format-standard","has-post-thumbnail","category-agentic-ai","tag-agentic-ai","tag-agentic-artificial-intelligence","tag-ai-and-big-data","tag-chip-design","tag-multi-physics","tag-quantum-computing"],"_links":{"self":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/136515","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/comments?post=136515"}],"version-history":[{"count":0,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/136515\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media\/136516"}],"wp:attachment":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media?parent=136515"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/categories?post=136515"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/tags?post=136515"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}![\"Leading-edge](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/HAV_Article_1_thumbnail_600x340.jpg\")
<\/a><\/p>\n![\"Unstacking](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/3DIC-thumbnail.png\")
<\/a><\/p>\n![\"Safeguarding](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/MessyDataSlideThumbnail_600x340.png\")
<\/a><\/p>\n![\"The](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/DAC-2026-Sunday-evening-opening-talk-audience-image_nitin-dahad.jpg\")
The opening-night talk by Tim Costa of Nvidia drew a standing-room-only crowd. (Source: Nitin Dahad | EE Times)<\/p>\n![\"Nvidia\u2019s](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/Tim-Costa-Nvidia-on-stage-opening-night-DAC-2026-image_nitin-dahad.jpg\")
Nvidia\u2019s Tim Costa marked the company\u2019s debut at the DAC conference. (Source: Nitin Dahad | EE Times)<\/p>\n![\"Maieutic](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/Ashish-Lachhwani-at-DAC-2026-image_nitin-dahad-e1786482810144.jpg\")
Maieutic Semiconductors\u2019 co-founder Ashish Lachhwani (Source: Nitin Dahad | EE Times)<\/p>\n![\"The](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/Synopsys-executive-panel-at-DAC-2026-image_nitin-dahad.jpg\")
The Synopsys executive panel at DAC in Long Beach, California. From left to right, Synopsys\u2019s Prith Banerjee, Microsoft\u2019s Marc Tremblay, Nvidia\u2019s Kari Briski, Qualcomm\u2019s Paul Penzes, and Synopsys\u2019s John Lee (Source: Nitin Dahad | EE Times)<\/p>\n![\"John](\"https:\/\/www.europesays.com\/ai\/wp-content\/uploads\/2026\/08\/John-Martinis-quantum-talk-at-DAC-2026-image_nitin-dahad.jpg\")
John Martinis, 2025 Nobel Prize winner in Physics and CTO and co-founder of Qolab, giving the opening keynote at DAC 2026 (Source: Nitin Dahad | EE Times)<\/p>\n