6.25| Power Supply for Gate Driver and E-mobility <\/a> <\/p>\nA response to growing complexity<\/p>\n
The rise of AI agents is not simply about replacing manual work, Cunningham emphasized. Instead, it is becoming a practical necessity as semiconductor complexity continues to outpace the industry\u2019s ability to recruit and train engineers.<\/p>\n
\u201cThe future will be a world where the productivity is another 10X compared to today,\u201d he said. \u201cIf we don\u2019t have agents, then we would need to hire 10 times the people because the semiconductor industry is growing so fast and the complexity is growing so fast.\u201d<\/p>\n
The challenge extends beyond headcount. Advanced semiconductor development increasingly demands specialized expertise across architecture, design, verification, packaging, software and system integration. Even aggressive hiring efforts cannot fully address those requirements.<\/p>\n
Cunningham likened the situation to baking bread, which is a hobby of his. Regardless of how many ovens are available, baking still requires a fixed amount of time. Likewise, semiconductor development eventually reaches limits that cannot be solved simply by adding engineers.<\/p>\n
\u201cAt some point, we need to really move faster,\u201d he said. \u201cAnd I think agents can move faster than humans.\u201d<\/p>\n
How to achieve a 10X productivity gain<\/p>\n
Cadence sees two primary mechanisms for achieving major productivity improvements.<\/p>\n
The first is automating repetitive engineering tasks. Much of an engineer\u2019s daily work involves analysis, debugging, searching through documentation, and resolving issues that often resemble previous problems. These activities are well suited to agent-based automation.<\/p>\n
The second is a higher level of abstraction.<\/p>\n
Just as software developers increasingly describe requirements and allow AI systems to generate code, Cunningham expects chip development to move toward specification-driven design. Engineers will focus more on defining intent and architecture, while agents generate RTL, schematics and implementation details.<\/p>\n
\u201cInstead of writing the Python program or the Java program, you actually write a specification,\u201d he said. \u201cI think chip design will have the same.\u201d<\/p>\n
The underlying design languages may differ\u2014SystemVerilog, Verilog, VHDL and analog design environments rather than software languages\u2014but the principle remains the same: translating specifications into implementation through AI-assisted automation.<\/p>\n
The productivity challenge becomes even more pronounced as the industry adopts chiplet-based architectures, advanced packaging, and 3D IC integration.<\/p>\n
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According to Cunningham, today\u2019s design teams must simultaneously address increasingly difficult physical and logical challenges.<\/p>\n
On the physical side, engineers must model thermal behavior, electromigration, warpage, mechanical stress and other multi-physics effects across complex heterogeneous systems.<\/p>\n
This trend is driving convergence between traditional chip design and physics-based simulation disciplines.<\/p>\n
\u201cThermal, EM, warpage, stress\u2014all of these come more from the physical world,\u201d Cunningham said. \u201cThat\u2019s why we\u2019ve been investing and growing what we call our System Design and Analysis group.\u201d<\/p>\n
On the logical side, teams must determine how functions are partitioned across multiple dies and then verify that the resulting system behaves correctly.<\/p>\n
Verification itself is becoming significantly broader in scope.<\/p>\n
\u201cCustomers don\u2019t just want to emulate now the single chip,\u201d Cunningham explained. \u201cThey want to emulate the entire rack.\u201d<\/p>\n
As AI servers increasingly consist of interconnected processors, accelerators, memory subsystems and networking components, verification must encompass complete systems rather than individual devices.<\/p>\n
AI in digital design<\/p>\n
While Cunningham believes AI will eventually transform every stage of semiconductor development, digital front-end design currently appears to be moving fastest.<\/p>\n
The reason is straightforward: writing RTL shares similarities with software development, where generative AI has already demonstrated significant productivity gains.<\/p>\n
\u201cWe have the most success so far with our ChipStack agent,\u201d he said.<\/p>\n
That advantage may be temporary. Cadence is simultaneously developing agentic workflows for digital implementation, physical design, 3D IC development and analog design.<\/p>\n
The timelines separating these domains are measured in months rather than years.<\/p>\n
\u201cIt is not much different\u2014three to six months behind,\u201d Cunningham said. \u201cEverything is kind of going in parallel.\u201d<\/p>\n
Here come \u201cSuper agents\u201d <\/p>\n
A recurring question facing the EDA industry is whether general-purpose AI assistants will eventually eliminate the need for specialized EDA platforms.<\/p>\n
Cunningham\u2019s answer is clear: no.<\/p>\n
According to him, achieving Level 5 autonomy in chip design requires substantially more than connecting an LLM to engineering data.<\/p>\n
Design and verification tasks involve massive amounts of information, complex workflows and numerous validation steps. Large tasks must be decomposed into smaller activities, executed in sequence and continuously verified using established EDA tools.<\/p>\n
As a result, Cadence views a super agent almost as a new category of EDA software.<\/p>\n
\u201cTo build this system itself, it requires a lot of programming,\u201d Cunningham said. \u201cI actually think that a super agent for chip design is almost like another EDA tool.\u201d<\/p>\n
The company believes this complexity creates a durable advantage for EDA vendors. Just as semiconductor companies eventually stopped building and maintaining their own internal EDA environments, Cunningham expects most customers to rely on commercial suppliers for autonomous engineering platforms.<\/p>\n
\u201cThe general-purpose agents will not be enough,\u201d he said.<\/p>\n
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Keeping AI trustworthy<\/p>\n
Despite enthusiasm surrounding autonomous design, semiconductor development remains unforgiving. A single design error can jeopardize an entire tapeout.<\/p>\n
For that reason, Cadence does not envision AI replacing traditional engineering validation.<\/p>\n
Instead, Cunningham described a model in which agents handle exploration, debugging, iteration and optimization, while final approval remains anchored in established sign-off methodologies.<\/p>\n
\u201cThe agent always needs to check with our proven engineering-based software that it is correct and safe,\u201d he said.<\/p>\n
The industry\u2019s sign-off process, built on deterministic physics-based and engineering-based tools, remains unchanged.<\/p>\n
\u201cWe will not change the signature,\u201d Cunningham added. \u201cWe will just make it more efficient to get to the point where we can sign.\u201d<\/p>\n
Rooted in physics<\/p>\n
Cadence\u2019s strategy differs from approaches that focus primarily on large language models.<\/p>\n
The company continues to invest heavily in simulation, physics-based modeling and optimization technologies, viewing them as complementary rather than competitive with AI.<\/p>\n
\u201cAI is very powerful, but it\u2019s not the answer for everything,\u201d Cunningham said.<\/p>\n
He believes future EDA systems will combine LLMs with traditional scientific algorithms, creating workflows in which AI orchestrates tasks while engineering engines provide trusted analysis and validation.<\/p>\n
The company also expects multi-model AI deployments to become increasingly important. Different LLMs may be assigned to different tasks based on performance, specialization and cost considerations.<\/p>\n
\u201cTokens are very expensive,\u201d Cunningham noted. \u201cHaving a multi-LLM strategy is also really critical to be cost efficient.\u201d<\/p>\n
Inside ChipStack<\/p>\n
At the core of ChipStack are two technologies that Cadence considers differentiators.<\/p>\n
The first is a proprietary knowledge graph that Cunningham describes as a \u201cmental model,\u201d a structured representation that serves as a single source of truth for the design. The system ingests specifications, source code and design information, organizing them into a structured representation of relationships, interfaces and dependencies.<\/p>\n
This allows the ChipStack agents to retrieve relevant design context, reason more consistently when performing tasks or responding to engineering questions.The second element is what Cadence calls \u201cnative skills.\u201d<\/p>\n
This native skills framework gives ChipStack a tool-calling layer to invoke Cadence EDA tools, interpret engineering feedback, and drive closed-loop decision making across verification workflows.<\/p>\n
If verification coverage is insufficient, for example, the agent can invoke Cadence tools, analyze the results and refine its approach accordingly.<\/p>\n
\u201cThe mental model and the Cadence Native Skills are the two technologies in ChipStack,\u201d Cunningham said.<\/p>\n
Engineers remain in the loop<\/p>\n
Although Cadence promotes increasing levels of autonomy, Cunningham does not envision a fully human-free design process.<\/p>\n
ChipStack includes user interfaces that expose reasoning, conclusions and intermediate actions, making it easier for engineers to review the agent\u2019s work.<\/p>\n
Human oversight, combined with traditional verification and sign-off tools, remains central to maintaining design quality.<\/p>\n
\u201cHuman review is made very easy with ChipStack,\u201d he said.<\/p>\n
Meanwhile, as agentic AI becomes mainstream, concerns about job displacement are inevitable. Cunningham takes a longer-term view.<\/p>\n
Historically, he argued, productivity gains have expanded industries rather than eliminated them. New tools enable engineers to tackle larger and more ambitious problems.<\/p>\n
\u201cI absolutely believe agents can do the work of many people,\u201d he said. \u201cSo, we will just write more complex software, we will innovate more.\u201d<\/p>\n
For now, Cunningham views today\u2019s AI systems as powerful tools rather than artificial general intelligence. While they can automate substantial portions of engineering work, they remain fundamentally different from human cognition.<\/p>\n
That distinction underpins his optimism about the industry\u2019s future.<\/p>\n
The semiconductor sector is entering an era defined not only by AI data centers, but also by autonomous vehicles, robotics and increasingly intelligent physical systems. Meeting those opportunities will require far greater engineering productivity than current methodologies can provide.<\/p>\n
For Cadence, the transition from EDA tools to AI super agents represents the next step in that evolution.<\/p>\n
\u201cI think it is a really exciting time,\u201d Cunningham said. \u201cThe semiconductor industry has just so many amazing opportunities still to change the world even more.\u201d<\/p>\n
\u00a0<\/p>\n
Stephen Las Marias is the editor of EE Times Asia\/India and EDN Asia. He can be reached at stephen.lasmarias@aspencore.com<\/a>.<\/p>\n\u00a0<\/p>\n","protected":false},"excerpt":{"rendered":"For decades, electronic design automation (EDA) has been built around a simple objective: helping engineers design increasingly complex…\n","protected":false},"author":2,"featured_media":82594,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[6],"tags":[405,7537,10595,41880,31549,41881,41882],"class_list":["post-82593","post","type-post","status-publish","format-standard","has-post-thumbnail","category-agentic-ai","tag-ai-agents","tag-artificial-intelligence-agents","tag-cadence","tag-chipstack","tag-computex-2026","tag-innostack","tag-virastack"],"_links":{"self":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/82593","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/comments?post=82593"}],"version-history":[{"count":0,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/82593\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media\/82594"}],"wp:attachment":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media?parent=82593"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/categories?post=82593"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/tags?post=82593"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
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