recruited a new executive<\/a> to lead advanced packaging. Applied Materials, the biggest maker of chip manufacturing tools, is building a $5 billion research facility in Silicon Valley with partners, with packaging as a key sideline.<\/p>\nAmkor Technology, a packaging specialist, is building its first U.S. factory site in Arizona and is expected to take on some packaging work for TSMC under a 10-year deal. Amkor, which the Biden administration awarded a $407 million grant, boosted its own potential investment on the site to $7 billion after talks with Trump administration officials and signs of purchasing interest from Nvidia and Apple.<\/p>\n
Such customers are showing \u201cvery strong demand, wanting to build a U.S. ecosystem,\u201d said Kevin Engel, Amkor\u2019s president and chief executive.<\/p>\n
Packaging was long considered an afterthought that U.S. chip makers farmed out to countries in Asia with low wages. The U.S. share of chip packaging is around 3 percent, according to the Global Electronics Association.<\/p>\n
Chips don\u2019t work without packaging. The process, also called assembly, typically wraps bare pieces of silicon in protective plastic with connectors to pass signals to other chips on a circuit board.<\/p>\n
These days, chips are frequently placed on an intermediary layer called a substrate, which is typically made of plastic and glass fiber and embedded copper wiring.<\/p>\n
Dr. Iyer, who earned a doctorate at U.C.L.A. before joining IBM in 1981, pushed another key advance. At IBM, he developed one of the first \u201cinterposers,\u201d a layer made from silicon that holds multiple chips side by side and sends signals between them at greater speeds.<\/p>\n
For the larger packages that some A.I. processors need, TSMC and Intel embed small pieces of silicon in substrates to act as communication bridges between chips.<\/p>\n
\u201cYou can\u2019t make them without advanced packaging,\u201d said Mark Gardner, an Intel vice president and general manager for packaging and testing. \u201cWe\u2019d be in a very different place in the A.I. world without it.\u201d<\/p>\n
TSMC offers advanced packaging called CoWoS, short for chip on wafer on substrate. Nvidia\u2019s new Rubin processor, for example, uses CoWoS to bundle two large A.I. chips with eight stacks of high-speed memory that each contain 12 chips, amassing 336 billion transistors in one package. By 2029, TSMC predicts a 48-fold boost in computing transistors per package compared with 2024.<\/p>\n
But the company, which received CHIPS Act funding to build major chip factories in Arizona, doesn\u2019t plan to use CoWoS in the state until 2028 or 2029. Any chips it makes there now must be sent to Taiwan for packaging.<\/p>\n
TSMC is already struggling to catch up with A.I.-driven orders. Its CoWoS production is about 30 percent short of demand, estimated Handel Jones, an analyst at International Business Strategies, who said TSMC accounted for about 95 percent of all advanced packaging.<\/p>\n
\u201cAll I see is demand continuing to go higher and higher,\u201d said Kevin Chang, a TSMC senior vice president. \u201cIt is certainly going to cause a lot of constraints.\u201d<\/p>\n
And costs remain high. An advanced chip package may cost $500, said Jan Vardaman, president of the research firm TechSearch International. Simpler packages may cost closer to $40, industry executives said.<\/p>\n
Some chip start-ups are deliberately avoiding designs relying on CoWoS, which can require months to design the required interposer.<\/p>\n
\u201cDidn\u2019t want to touch it,\u201d said Sha Rabii, a co-founder and the president of Majestic Labs, which is designing an A.I. processor that can use simpler packaging and cheaper memory chips. \u201cIt takes a key part of the supply chain challenge off the table.\u201d<\/p>\n
Over the long term, Dr. Iyer and industry executives said, there need to be new packaging concepts. Syenta, an Australian start-up, has proposed one that uses electrochemical techniques to create extra-large packages with fewer manufacturing steps and up to a twentyfold boost in communications bandwidth, said Jekaterina Viktorova, the company\u2019s chief executive.<\/p>\n
Others are marshaling partners for packaging research. Resonac, a Japanese chemical maker, recently announced a 12-company packaging consortium and pilot production line near Silicon Valley.<\/p>\n
But government support remains uncertain. The Biden administration had designated a nonprofit, Natcast, to oversee $7.4 billion in research funding from the CHIPS Act, with packaging as a focus candidate.<\/p>\n
In 2023, Dr. Iyer joined the Commerce Department\u2019s chip program, devising a plan for a facility where researchers could develop and test new semiconductor materials, chips and packaging. He returned to U.C.L.A. in the fall of 2024.<\/p>\n
The Commerce Department didn\u2019t announce the facility\u2019s proposed funding and location, at an Arizona State University research park, until January 2025. Under Mr. Trump, there was little action until Commerce Secretary Howard Lutnick declared that Natcast<\/a> was an illegally created organization that August and clawed back its funding. The group disputed that claim but disbanded last fall.<\/p>\nNot all industry executives are mourning the would-be Arizona packaging facility. Mr. Gelsinger, now a general partner at the venture capital firm Playground Ventures, contends it should have been at an existing research facility rather than started from scratch.<\/p>\n
Dr. Iyer, who wasn\u2019t involved in the site selection, agreed. But he added: \u201cI thought I put together a good program. I did not expect it to fall apart.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"Subramanian Iyer, an electrical engineer and educator, has long specialized in a sleepy niche of the semiconductor industry…\n","protected":false},"author":2,"featured_media":86793,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[2],"tags":[24,841,845,25,4868,15589,1555,46352,684,26897,46353,1925,38272,1576,18451],"class_list":["post-86792","post","type-post","status-publish","format-standard","has-post-thumbnail","category-ai","tag-ai","tag-amkor-technology-inc","tag-applied-materials-inc","tag-artificial-intelligence","tag-commerce-department","tag-computer-chips","tag-computers-and-the-internet","tag-factories-and-manufacturing","tag-innovation","tag-intel-corporation","tag-international-business-machines-corporation","tag-los-angeles","tag-taiwan-semiconductor-manufacturing-company-ltd","tag-united-states-politics-and-government","tag-university-of-california"],"_links":{"self":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/86792","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/comments?post=86792"}],"version-history":[{"count":0,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/posts\/86792\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media\/86793"}],"wp:attachment":[{"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/media?parent=86792"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/categories?post=86792"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.europesays.com\/ai\/wp-json\/wp\/v2\/tags?post=86792"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}