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Post-quantum semiconductor and digital identity developer SEALSQ Corp (NASDAQ: LAES)<\/a> has announced an engineering update on QASIC (Quantum-Resistant Application-Specific Integrated Circuit), its sovereign post-quantum ASIC<\/a> platform developed through its French chip design subsidiary, IC\u2019Alps<\/a>.<\/p>\n The initiative embeds hardware-accelerated Post-Quantum Cryptography (PQC) directly into customer-owned, application-specific silicon architectures. The joint engineering track remains on schedule to deliver its first functional prototype in 2026.<\/p>\n [ SEALSQ \/ IC\u2019Alps QASIC Integrated Platform Architecture ]PQC Semiconductor OfferingIC\u2019Alps Design & IP CapabilitiesTarget Sectors & Deployment\u2022 Catalog PQC Integrated Circuits\u2022 RISC-V SoC Infrastructure & Functional Safety\u2022 Cybersecurity & HSMs\u2022 Custom QASICs & Reusable IP\u2022 Ultra-Low Power Analog & Mixed-Signal Design\u2022 Connected Medical & Diagnostics\u2022 Chiplet Hardware Security Modules\u2022 Certified Production & Foundry Ecosystem\u2022 SDVs, Autonomous Driving & V2X<\/p>\n Embedding Post-Quantum Security at the Silicon Level<\/p>\n Standard microcontrollers and classical Hardware Security Modules (HSMs) rely on public-key algorithms (such as RSA and ECC) vulnerable to quantum decryption. The QASIC framework combines SEALSQ\u2019s post-quantum root-of-trust IP with IC\u2019Alps\u2019 mixed-signal and analog ASIC capabilities to support three target markets:<\/p>\n Cybersecurity & Infrastructure: Secure microcontrollers, identity authentication engines, secure communications, data protection, and critical infrastructure HSMs.<\/p>\n Medical & Healthcare Devices: Implantable devices, connected diagnostic equipment, patient monitors, and healthcare data security.<\/p>\n Automotive Systems: Software-Defined Vehicles (SDVs), autonomous driving compute units, Vehicle-to-Everything (V2X) communications, secure Over-the-Air (OTA) updates, and telematics.<\/p>\n Integrated Product Portfolio and Global Foundry Ecosystem<\/p>\n QASIC operates as part of SEALSQ\u2019s three-tier post-quantum hardware architecture:<\/p>\n Catalog Integrated Circuits: Standard off-the-shelf security microcontrollers incorporating pre-certified PQC IP.<\/p>\n Custom ASICs & Reusable IP: Fully customized QASIC implementations designed around specific customer power, latency, and area (PPA) constraints.<\/p>\n Chiplet-Based Security Architectures: Next-generation Chiplet-based Hardware Security Modules (CHSMs) integrating pre-certified secure enclaves.<\/p>\n IC\u2019Alps contributes domain expertise across RISC-V-based System-on-Chip (SoC) architectures, embedded non-volatile memory, functional safety (ISO 26262), and power management. The subsidiary manages production across a global semiconductor foundry network, including TSMC<\/a>, GlobalFoundries<\/a>, STMicroelectronics<\/a>, Intel Foundry<\/a>, X-FAB<\/a>, and ams-OSRAM<\/a>.<\/p>\n Led by SEALSQ CEO Carlos Moreira<\/a> and IC\u2019Alps General Manager Jean-Luc Triouleyre<\/a>, the QASIC platform anchors SEALSQ\u2019s broader \u201cQuantum Corridor,\u201d linking semiconductor engineering across Switzerland, France, Spain, the U.S., Korea, and the UAE.<\/p>\n Review the announcement on GlobeNewswire here<\/a>, and examine our previous coverage of SEALSQ Announces QASIC Initiative to Develop Quantum-Resistant ASICs with IC\u2019Alps here<\/a>, SEALSQ Boosts Quantum Investment Fund to Over $100 Million for European Sovereignty here<\/a>, and SEALSQ Acquires Miraex to Finalize Quantum Sovereign Vertical Stack here<\/a>.<\/p>\n August 26, 2026<\/p>\n
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