Samsung Electronics and a research team from Pohang University of Science and Technology (POSTECH) in South Korea have developed a core technology poised to push beyond the stacking limits of 3D NAND memory semiconductors. The breakthrough addresses the problem of increasing resistance in data transmission pathways as the number of vertically stacked cell layers rises, by controlling the direction of crystal growth.
POSTECH announced on the 7th that Professor Hyunsang Hwang of the Department of Materials Science and Engineering and Semiconductor Engineering, along with integrated program researcher Oh-hyeok Kwon, secured the technology to control the growth direction of silicon crystals inside 3D NAND channels through joint research with Samsung Electronics’ Semiconductor R&D Center and Memory Business. The achievement was presented at the 2026 IEEE International Symposium on VLSI Technology and Circuits, one of the most prestigious academic conferences in the semiconductor field, and was selected as a Research Highlight in the international journal Nature Electronics.
3D NAND is a non-volatile memory used in smartphones, USB drives, and data center storage devices. To increase storage capacity, cells that hold information are stacked vertically up to hundreds of layers. However, as stacking increases, the vertical pathway for data—the “silicon channel”—lengthens, causing channel resistance to rise and degrading data processing speed and read performance.
Metal-induced lateral crystallization (MILC) has drawn attention as a method to solve this problem. It is a technique that uses nickel as a catalyst to create high-quality silicon crystals at relatively low temperatures. However, its limitation has been the difficulty in controlling the direction of crystal growth; needle-like crystals grow in random directions and stop growing when they collide with each other, leaving nickel residue inside the channel.
The research team solved this problem by introducing a “seed layer” at the starting point of crystal growth to guide its direction. The method involves forming a thin nickel film on a silicon substrate and then applying microwave annealing. Just as a microwave oven delivers heat to specific molecules inside food, the process selectively concentrates energy only at the interface where nickel and silicon meet, inducing the crystals to grow in a uniform direction.
When this seed layer was applied to the surface of a 3D NAND channel, the crystals extended in a single direction without spreading randomly. The team successfully applied this technology to an actual 155-layer 3D NAND structure, creating uniformly aligned crystals from the top to the bottom of the channel.
As the industry intensifies its stacking competition to secure greater storage capacity, this research is seen as laying the groundwork for simultaneously lowering channel resistance while securing performance and power efficiency. “We have presented a practical solution that can uniformly crystallize the entire channel even in next-generation 3D NAND with increasing layer counts,” explained Professor Hyunsang Hwang.
Samsung Electronics is accelerating its next-generation NAND technology development, recently unveiling the industry’s first 10th-generation V-NAND “V10 BV-NAND” with over 400 vertically stacked layers at FMS 2026 in the United States, along with its high-performance NAND solution “zNAND-O.” This research achievement was made possible through Samsung Electronics’ industry-academia joint research support program.