TSMC has scored another victory in the angstrom-class semiconductor process race. Industry sources indicate that TSMC has successfully developed and validated its A16 process technology, becoming the world’s first foundry to integrate a “Super Power Rail” (SPR) backside power delivery architecture into an angstrom-class CMOS platform. This breakthrough gives TSMC a critical lead in advanced process technology below 2 nanometers.

The A16 process is scheduled to enter volume production in the fourth quarter of this year and is viewed as a key strategic initiative for TSMC in the AI and high-performance computing (HPC) chip market.

Backside Power Delivery: Breaking Through Frontside Routing Bottlenecks

As semiconductor processes continue to shrink, traditional chip designs place both power delivery interconnects and signal interconnects on the frontside of the chip, where the two compete for limited routing space. As process nodes advance below 2 nanometers, routing congestion has become increasingly severe, and voltage drop (IR Drop) caused by rising resistance has emerged as a critical bottleneck affecting chip performance.

The core concept of backside power delivery technology is to move the power distribution network entirely from the frontside to the backside of the chip, freeing up frontside space for signal routing. However, integrating backside power delivery has historically required substantial adjustments to transistor layouts and standard cell structures. In advanced processes, it has even been necessary to abandon portions of existing cell libraries and design methodologies, creating design compatibility issues.

The key breakthrough of TSMC’s A16 process lies in its preservation of the gate density and NanoFlex design flexibility of the N2P process. N2P is the enhanced version of TSMC’s N2 process. A16 builds on this foundation by completely separating the power delivery path to the backside of the chip, connecting directly to the source and drain of each transistor through dedicated vertical backside contacts (VB).

Industry sources note that under this architecture, TSMC has made only “minimal” adjustments to the frontside gate structure, cell dimensions, and layout area, thereby maintaining compatibility with existing chip designs. This means customers can directly enjoy the performance benefits of backside power delivery without redesigning their chip architectures.

Significant Performance Gains Targeting AI and HPC Markets

In terms of performance, A16 offers clear advantages over N2P. According to industry data, at the same power level, A16 delivers 8% to 10% higher computing speed; at the same computing speed, power consumption can be reduced by 15% to 20%, with chip density improving by 8% to 10% as well.

Performance MetricA16 Improvement vs. N2PComputing speed (same power)8% to 10% increasePower consumption (same speed)15% to 20% reductionChip density8% to 10% increase

Note: Data sourced from process performance comparisons provided by industry sources.

This dual improvement in performance and energy efficiency is particularly well-suited for AI accelerators and high-performance computing chips. These chips require complex signal routing and high-density power networks, and traditional frontside power delivery architectures have increasingly become a bottleneck for performance gains. One industry source noted that this technological breakthrough helps improve efficiency while reducing the design burden for products such as AI accelerators, especially since these chips must balance energy efficiency with computing performance.

Competitive Landscape: Intel and Samsung in Pursuit

The commercialization race for backside power delivery technology has entered a white-hot phase. Intel (INTC) was the earliest entrant in this field, and its PowerVia backside power delivery technology has been integrated into the Intel 18A process for volume production. However, reports indicate that Intel had to modify its existing cell architecture during the testing phase, including adjusting pin counts, relaxing metal pitch, and redesigning cell structures.

South Korea’s Samsung Electronics (005930.KS) is also developing backside power delivery technology for its SF2 process. Industry sources indicate that Samsung’s approach may be similar to Intel’s, meaning that integrating backside power delivery could require more substantial adjustments to existing design architectures.

By contrast, TSMC’s A16 process achieves backside power delivery integration while maintaining existing design compatibility, which the industry views as a significant technological differentiator. This not only reduces customers’ design migration costs but also accelerates time-to-market.

Shifting Competitive Focus in the Angstrom-Class Era

In the angstrom-class process era, industry competition is no longer confined to process technology itself. The design ecosystem is emerging as a new competitive battleground. TSMC’s A16 process, through its strategy of minimizing design changes, effectively protects customers’ existing design investments while delivering significant performance improvements—a strategically important advantage in the fiercely competitive AI chip market.

As the A16 process enters volume production in the fourth quarter of this year, TSMC’s leadership position in the angstrom-class process race is expected to be further consolidated. Market observers believe that if A16’s production ramp proceeds on schedule, it will establish a favorable foundation for TSMC in securing advanced process orders from the second half of 2026 through 2027, particularly in high-growth application areas such as AI accelerators and high-performance computing chips.