South Korea’s SK Hynix (000660.KS) on August 20 jointly published a paper with researchers from the University of Virginia and other institutions in the prestigious scientific journal Nature Electronics, systematically outlining the development roadmap for Co-Packaged Optics (CPO) technology in high-performance computing and artificial intelligence. This marks the first time SK Hynix has publicly disclosed its AI interconnect architecture blueprint in a journal of this caliber. The paper proposes a long-term vision that goes a step further than current industry discussions: extending optical interconnects from between processors all the way to memory interfaces.
The paper notes that High Bandwidth Memory (HBM) has addressed memory bottlenecks within chips, but as AI clusters scale to thousands of GPUs, data transmission between racks has become the new constraint. Data shows that compute power grows approximately 3x every two years, while interconnect bandwidth grows only about 1.4x over the same period. This divergence creates what the paper calls the “Bandwidth Wall”—a core bottleneck for AI scaling.
Traditional copper-based electrical interconnects still hold cost advantages over short distances, but as transmission speeds increase and distances grow, signal loss and power consumption rise sharply, requiring increasingly complex compensation circuitry and adding latency. Kyusang Lee, a professor in the Department of Electrical and Computer Engineering at the University of Virginia and one of the paper’s corresponding authors, stated bluntly: “Even if computing chips become more powerful, overall system performance cannot improve if data transmission between chips cannot keep pace. Replacing copper interconnects—which face inherent physical limitations—with optical interconnects is the most promising path to future scalability.”
The core concept of CPO is to integrate optical transceivers (TRx) into the same package as the processor, enabling chips to exchange data via optical signals rather than long-distance electrical signals. The distance over which high-speed electrical signals must travel is compressed to a minimum, with the remaining path handled by optical links—preserving the efficiency of intra-package electrical interconnects while leveraging the low-loss characteristics of light for high-speed transmission across chips, racks, and clusters.
The paper sets clear technical targets for next-generation AI infrastructure: per-node bandwidth exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and chip-to-chip latency under 10 nanoseconds. The research team also mapped out the evolution path of CPO from 2D and 2.5D interposer configurations to 3D heterogeneous stacking, itemizing the key technical challenges that must be overcome for commercial deployment.
Extending Optical Interconnects to Memory Interfaces
The paper’s most groundbreaking proposal is an “optics-centric” architecture that uses a photonic interposer to directly connect a processor resource pool (XPU pool) with a memory resource pool. This means multiple AI accelerators can share a single large-capacity memory pool rather than each being equipped with its own dedicated memory, breaking through the physical constraints of existing packaging.
Kyusang Lee explained: “Extending optical interconnects to memory interfaces will break through the physical constraints surrounding compute chips, removing limitations on memory capacity and the number of electrical connections.” Seunghoon Hong, the other corresponding author and head of SK Hynix’s AI Infrastructure team, added: “The biggest advantage is that by improving data movement efficiency, AI systems can scale more flexibly. This ultimately provides customers with a foundation for operating AI infrastructure more efficiently.”
Other institutions involved in the research include the University of Illinois Urbana-Champaign (UIUC), Nanyang Technological University (NTU), the Massachusetts Institute of Technology (MIT), and Yonsei University.
From HBM Supplier to System Architecture Participant
HBM has solved the memory bandwidth problem within AI accelerator packages and has been the core competitive strength of SK Hynix over the past several years. The release of the CPO roadmap signals that the company is extending its technology portfolio from individual components to system-level architecture.
Hong articulated this shift clearly in an interview: “Memory companies are evolving from the role of providing individual components to becoming partners that help enhance the competitiveness of customers’ entire systems through technologies like CPO.”
Kyusang Lee also emphasized the indispensability of academia-industry collaboration: “Academia excels at pushing performance boundaries, while industry understands the practical requirements of large-scale deployment—including manufacturing yield, cost, thermal management, and supply chain. Only by combining these two perspectives can a practical roadmap be developed.” He also acknowledged that the path to commercialization still faces significant challenges: “From integrating low-power photonic devices to developing coherence protocols and improving system reliability, the challenges remain substantial. The key lies in co-designing memory devices with controllers, photonic components, and packaging as an integrated system.”
Market Reaction
On the day of the paper’s publication, SK Hynix shares surged more than 11%, driven by the CPO paper and share buyback program news. CPO concept stocks in Taiwan and China rallied in tandem: Chinese optical component maker T&S Communications (300570.SZ) rose over 12%, China Circuit Technology (002579.SZ) hit the daily limit-up, and Chinese vendors TZTEK Technology (688003.SS), Shijia Photons (688313.SS), Deca Technologies (688205.SS), and Linktel Technologies (301205.SZ) all gained more than 6%.
CPO is viewed by the industry as a critical path to breaking through the “bandwidth wall” in AI infrastructure. Major semiconductor players including TSMC (2330.TW), Intel, and Broadcom are all actively investing in CPO technology. SK Hynix’s public disclosure of its technology blueprint in a prestigious journal signals that memory giants are also aggressively positioning themselves in the optical interconnect space. Going forward, competition in AI system architecture will extend from single-chip performance to system-level integration capabilities spanning memory, packaging, and optical interconnects.