Samsung Electronics’ foundry division is accelerating validation of its 2-nanometer (nm) process and efforts to escape losses, using orders for Tesla’s next-generation autonomous driving and AI chips as a springboard. At the same time, SK Hynix has unveiled a blueprint for next-generation optical interconnect technology through a world-renowned academic journal, signaling an expansion of the memory company’s role in addressing bandwidth bottlenecks in hyperscale AI infrastructure.

◆ Samsung Foundry Secures Taylor Fab Utilization With Tesla 2nm Chips

Samsung Electronics’ foundry division is concentrating on tape-out and pilot production preparation for Tesla’s next-generation autonomous driving and AI chips, the “AI5” and “AI6,” to prove the reliability of its gate-all-around (GAA) based 2nm process. The leading-edge volume bound for Tesla, estimated at approximately 20 trillion won (approximately $14.5 billion), is expected to enter full-scale mass production starting in 2027.

Chips for autonomous driving and supercomputers demand extreme thermal control and computational accuracy, as vehicle stoppages or malfunctions can directly lead to fatal accidents. Stable mass production supply of Tesla’s chips is expected to serve as a key indicator validating Samsung Foundry’s process technology capabilities.

Analysts note that securing Tesla as an anchor customer and completing production validation could lead to additional orders from global fabless customers such as Nvidia and Qualcomm, which have been waiting on the sidelines regarding 2nm yields. This is the critical link that will determine utilization rates and profitability at Samsung Electronics’ Taylor, Texas foundry fab, into which the company has invested more than $37 billion (approximately 51.2 trillion won).

The Tesla volume slated for 2027 must support baseline utilization of Phase 1 to ease the fixed-cost burden, creating a virtuous cycle that leads to the Phase 2 expansion investment targeted for 2030. The outlook is that leveraging Tesla orders to boost Taylor fab productivity and securing self-sustainability of the most advanced U.S. manufacturing base will determine the long-term success or failure of the foundry business.

◆ SK Hynix Publishes CPO Technology Roadmap in Nature

Following high-bandwidth memory (HBM), SK Hynix has unveiled a technology roadmap for “CPO (Co-Packaged Optics),” a next-generation optical interconnect designed to overcome data transmission limits in hyperscale AI clusters. The company published a CPO technology paper in the world-renowned journal Nature Electronics, co-authored with leading researchers from the University of Virginia, University of Illinois, MIT, Nanyang Technological University, and Yonsei University.

While generative AI compute performance has been increasing roughly threefold every two years, data transmission bandwidth has grown only 1.4-fold, making the “bandwidth wall” that restricts data movement between systems a chronic limitation of hyperscale AI clusters. CPO is a technology that integrates optical transceivers into a single package with compute chips and memory, enabling data exchange via light to overcome the signal attenuation and power consumption limits of traditional copper wiring connecting server racks.

This approach shortens the distance electrical signals must travel, securing wide bandwidth of over 100Tb/s per node while enabling ultra-low power consumption of under 1pJ per bit and low latency of under 10ns. The paper presents an architecture that extends optical connectivity beyond compute processors to memory interfaces, systematizing a structure in which multiple accelerators directly share a massive memory pool via optical signals.

This demonstrates that memory companies are evolving beyond simple component suppliers into core technology partners that enhance data movement efficiency across entire systems.

◆ HBM Competition Shifts From “Faster” to “Better Designed and Stacked”

Samsung Electronics and SK Hynix will each showcase different core HBM technologies at “Hot Chips 2026,” a semiconductor design conference held at Stanford University from the 23rd to the 25th. On the first day, the 23rd, Samsung Electronics’ PL Han Sang-wook will present on base die, while SK Hynix Vice President Lee Jae-sik will present on advanced packaging.

This year’s Hot Chips is notable for memory taking center stage. The very first tutorial session is titled “Memory Technology,” and a dedicated session has been arranged in the main conference as well. This reflects how memory, which supplies the exploding volumes of data processed by AI, has emerged as a critical factor determining performance.

Samsung Electronics will introduce the base die that sits at the bottom of HBM. This chip connects multiple DRAM dies to compute devices such as GPUs, serving as a conduit that sends stored data to the GPU and receives and relays necessary information back. Leveraging the strength of operating both memory and foundry businesses, Samsung Electronics applied a base die manufactured on its foundry’s 4nm process to HBM4, which entered mass production in February.

SK Hynix is focusing on packaging that “stacks and cools well.” On the same day, under the theme “Advanced Packaging for HBM,” the company will unveil solutions for reducing heat and warpage. Because HBM stacks DRAM dies layer by layer, taller stacks generate more heat and chips warp more easily. How stably these issues are managed determines performance and yield.

The flagship technology is “Advanced MR-MUF.” This method fills liquid protective material between stacked DRAM dies and cures it, firmly holding the chips while dissipating heat outward. It was also applied to the 12-high HBM4E supplied to major customers in June. Thermal resistance was reduced by 17% compared to HBM4, and maximum operating speed was raised to 16Gbps per pin.

The presentation topics chosen by the two companies illustrate how competition has become significantly more complex starting with HBM4. HBM4’s I/O (input/output) increased from HBM3E’s 1,024 to 2,048, doubling the data pathway width. As more information flows simultaneously, the importance of the base die that organizes this data has grown, and as different customers demand different HBM configurations, logic design and foundry process capabilities must be managed together. Heat becomes a bottleneck in the stacking process. As layer counts increase, heat generation rises and chips must become thinner; without controlling warpage and yield, even the fastest DRAM cannot deliver its full performance.

An industry insider said, “In the AI era, it has become difficult to view memory as a simple component,” adding, “South Korean companies are also moving beyond being chip suppliers to growing their role as partners who design AI systems together with customers.”