Samsung.com
Samsung Electronics presented working silicon of LPDDR5X-PIM at Hot Chips 2026 on Tuesday, demonstrating a mobile memory chip that handles AI matrix calculations inside the DRAM itself rather than ferrying weight data back and forth to a processor — and achieving three times the AI inference token throughput of conventional LPDDR5X in the same physical package that device makers already use, with no PCB redesign required. ServeTheHome published slide-by-slide live conference coverage of the full presentation.
The announcement landed at the annual semiconductor architecture conference held on the campus of Stanford University in Palo Alto, California, where Karam Hwang, a Samsung principal engineer who led the session, framed the pitch in economic terms: memory now accounts for more than 60 percent of total AI accelerator component costs, a share that climbed from 52 to 63 percent between the first quarter of 2024 and the end of 2025 — and is likely higher now. The chip is positioned as a lower-cost path to AI inference acceleration that doesn’t require the expensive, complex packaging that High Bandwidth Memory demands, a positioning Samsung’s Herald Business coverage connected directly to the phenomenon of chipflation.
Why Memory Costs Have Become the Binding Constraint
“HBM is currently the de facto standard for AI memory,” Hwang told conference attendees, “but as AI evolves toward inference-centric workloads and expands into devices like smartphones and AI PCs, a new memory form factor has become necessary.”
The problem Hwang described is structural. During AI inference — the process by which a language model generates outputs from a given input — a processor must repeatedly fetch the model’s weight parameters from memory for every token it produces. The weights live in DRAM; the math happens in the chip. That round-trip is slow, power-hungry, and, as models grow larger, increasingly the dominant cost in the whole operation. Computer architects call this the memory wall, a term coined by William Wulf and Sally McKee in their 1995 paper for ACM’s SIGArch newsletter, “Hitting the Memory Wall: Implications of the Obvious.”
High Bandwidth Memory emerged as one answer to the memory wall by stacking DRAM dies vertically and widening the bus to 2,048 bits in HBM4, but the solution carries its own costs: HBM consumes roughly three times the fabricated silicon area of conventional DRAM per gigabyte, and Micron — presenting a day earlier at the same conference — publicly quantified that compute TFLOPS outpace HBM bandwidth at nearly three times the growth rate, compounding through HBM8 in 2038. The gap will not close; it will compound.
LPDDR5X-PIM proposes a different approach: instead of moving data more efficiently, move far less data by computing directly where the weights already sit.
How LPDDR5X-PIM Actually Works
Processing-in-Memory is not a new concept — Samsung demonstrated HBM-PIM as early as 2021 with its Aquabolt-XL chip, integrating compute logic into High Bandwidth Memory stacks for use in the Xilinx Alveo AI accelerator. What LPDDR5X-PIM achieves for the first time is landing that same architecture inside the LPDDR-class memory that powers smartphones, laptops, and edge devices.
The architecture places one PIM compute block inside each of the chip’s 16 memory banks. That is an advance over the HBM-PIM design, where Samsung had to reduce bank count to accommodate the logic. Each PIM block contains a scale register file, a source register file, and parallel multiply-accumulate (MAC) trees — the fundamental arithmetic unit of neural network computation — with outputs flowing into a vector register file in either integer or floating-point format. The complete 16-bank MAC-tree architecture is detailed in Samsung’s Hot Chips slide package.
A MAC operation in PIM mode proceeds as follows: sixteen broadcast commands write 512 bytes of FP8 activation data across all sixteen banks simultaneously. A PIMX_RD command then reads weight data from the DRAM cell array, feeding it through the MAC trees alongside the activations from the source register file. The computed result lands in the vector register file. A PIMX_WR command moves that result back to the DRAM bank for storage. To retrieve the output, the host switches back to conventional single-bank mode and issues standard read commands. The entire cycle stays within the memory die — the processor never touches the intermediate weight data at all. Tom’s Hardware’s full MAC operation walkthrough illustrates each step with Samsung’s own slide diagrams.
The chip supports 15 selectable precision combinations through MAC precision fields in its configuration register, making it the first LP-PIM product with multi-precision support. Using SINT4 weights, the chip delivers 2.4 TOPS per package; in FP8, approximately 1.2 TFLOPs per package.
Drop-In Compatibility: The Engineering Unlock
The commercially decisive aspect of LPDDR5X-PIM is not its raw performance. It is the package. Samsung engineered the chip to use the same JEDEC-standard 561-ball array footprint as conventional LPDDR5X, with 16 GB of capacity across four dies per rank — identical on the outside to a standard memory module.
To make this work with an unmodified DRAM controller, Samsung developed a mechanism called Address Align Mode (AAM). The problem AAM solves is that a standard DRAM controller issues reads and writes against row and column addresses — it has no concept of MAC instructions. AAM maps DRAM addresses directly to MAC instruction register assignments, translating the row address to a vector register file address and the column address to a source register file address. The host can issue standard read or write commands, or switch to PIM read/write commands; the controller sees a familiar command interface either way. No new controller hardware is required. Tom’s Hardware’s AAM address-mapping explainer covers the VRF/SRF assignment logic in detail.
The mode change between conventional DRAM and PIM operation is handled via predefined rows and PIM registers. Samsung reported that this approach is faster and more reliable than the mode-switch mechanism used in the earlier HBM-PIM generation.
The result is that device makers with an existing LPDDR5X design can substitute LPDDR5X-PIM without changing a PCB trace, a controller register, or a system architecture decision — the PIM capability activates when software issues PIM commands, and the chip falls back to standard DRAM behavior otherwise.
By the Numbers: What Working Silicon Delivered
Samsung’s benchmark used Meta’s Llama 3.1 8B large language model running on its own edge AI accelerator SoC, with a 320-token context, SINT8 activations, SINT4 weights, and SINT32 output format.
MetricLPDDR5X (Standard)LPDDR5X-PIM
Package footprint
561-ball array
561-ball array (identical)
Capacity
16 GB
16 GB
Peak bandwidth (conventional interface)
76.8 GB/s
76.8 GB/s
PIM bandwidth
—
614 GB/s
Token throughput (TPS)
27.0 tokens/sec
81.3 tokens/sec (3.01×)
Task completion time (Llama 3.1 8B)
12.3 seconds
5.4 seconds (2.28× faster)
The 614 GB/s PIM bandwidth figure represents an 8× improvement over the 76.8 GB/s ceiling of standard LPDDR5X-9600 — achieved not by widening a bus or stacking more dies, but by eliminating most of the data movement that consumed that bandwidth in the first place. ServeTheHome’s evaluation results slide coverage shows the full benchmark methodology.
On power, Samsung said it does not expect net higher power consumption compared to conventional LPDDR5X. Peak power during PIM burst operations will be higher, Hwang acknowledged, but the dramatic reduction in round-trip data movement is expected to bring average power consumption at or below that of standard LPDDR5X. Tom’s Hardware confirmed Samsung’s power claims, noting Hwang’s statement that “We’re not having significant power increase.”
One open question raised by a conference attendee: the LPDDR5X-PIM results differ slightly from standard LPDDR5X outputs. Samsung confirmed the discrepancy and said optimizations are ongoing, with the company expressing confidence that accuracy improvements will not come at the cost of the demonstrated performance advantage. The accuracy gap is not quantified publicly.
How Samsung LPDDR5X-PIM Fits Into a Wider Memory Landscape
Samsung was explicit at Hot Chips 2026 that LPDDR5X-PIM is a complement to HBM, not a replacement. HBM offers raw bandwidth that LPDDR5X-PIM does not approach — HBM4 delivers up to 2 terabytes per second per stack versus LPDDR5X-PIM’s 614 GB/s total — and remains the standard for large-scale AI model training and high-throughput cloud inference.
What LPDDR5X-PIM addresses is the application tier that HBM cannot affordably reach: smartphones, AI PCs, and edge accelerators, where HBM’s cost, power draw, and packaging complexity are prohibitive. The market signal supporting this positioning is concrete: Nvidia’s Vera CPU already adopted LPDDR5X via SOCAMM2 serviceable memory modules, and Intel’s Crescent Island AI accelerator uses LPDDR5X as its primary memory — both products that could potentially benefit from the PIM-enabled version.
The competitive picture on LPDDR-class PIM is thin for now. SK Hynix has signaled plans for processing-in-module solutions targeting the next-generation LPDDR6 standard, expected around 2028. Micron has not announced an LPDDR-PIM roadmap. Samsung is alone with working silicon on the market today, which is a first-mover position in a segment that did not exist eighteen months ago.
Samsung GAIA: When LPDDR5X-PIM Leaves the Lab
The Hot Chips 2026 presentation was a technical disclosure. The commercial story that surrounds it involves a separate Samsung product that never appeared in the conference slides by name but that Tom’s Hardware noted the benchmark SoC “may be early GAIA”: Samsung’s GAIA, a 4nm AI accelerator being developed by its System LSI division specifically for AI PCs.
According to multiple reports citing Korean industry sources and corroborated by TrendForce and TechSpot, Samsung has already delivered GAIA prototype chips to Lenovo and HP for performance validation. Mass production is targeted for as early as 2027, with consumer devices potentially arriving in late 2027 or early 2028. TechSpot confirmed the HP and Lenovo validation program based on separate Korean industry sources.
GAIA is not a general-purpose processor. It is a companion accelerator — a chip that installs alongside whatever CPU a notebook already carries and handles AI inference workloads separately, with an NPU architecture optimized for generative AI tasks. What makes GAIA architecturally distinct from the Qualcomm Snapdragon X2 or Intel Core Ultra’s integrated NPU is that Samsung is co-optimizing GAIA with LPDDR5X-PIM from the start — a vertical integration play that no other AI PC silicon vendor can replicate without also manufacturing its own DRAM. gHacks’ GAIA companion processor explainer covers the Exynos division context and competitive positioning.
If GAIA reaches mass production as targeted, it will represent the first time PIM technology crosses from the research and validation stage into volume consumer silicon — and the first time the 3× inference throughput demonstrated at Hot Chips translates to something a person can buy in a laptop. Samsung has also separately disclosed that simulations of LPDDR5X-PIM in GEMV (general matrix-vector) operations — the core computation in transformer inference — showed up to 6.2× GEMV performance improvement versus conventional architectures, a figure exceeding the 3.01× measured in silicon benchmarks and suggesting that real-world performance improvements could widen as software matures.
What Comes Next for the LP-PIM Standard
Samsung’s Hot Chips 2026 presentation also addressed software infrastructure and standardization: a simulator and datasheet are available on request, and an SDK with reference tooling accompanies the chip for developers who want to begin workload mapping. LPDDR6-PIM, the next-generation form of the technology, is already moving toward a JEDEC specification — Samsung said it hopes to obtain an initial LP6-PIM spec from JEDEC before the end of 2026.
JEDEC had already signaled institutional support for LP-PIM in April 2026, when it previewed new LPDDR6 PIM features planned for the next version of JESD209-6 — its LPDDR6 standard — specifically to extend LPDDR6 beyond mobile platforms to support accelerated computing workloads. JEDEC standardization matters for a reason that Patrick Kennedy of ServeTheHome identified in his Hot Chips coverage: without a published, multi-vendor-accessible specification, memory customers depend entirely on a single supplier for both storage and compute — a concentration of leverage that has historically made buyers cautious. A finalized JEDEC LP6-PIM standard would open second-source competition and make the technology safe to build around for long-cycle-time products like laptops and edge infrastructure.
LPDDR5X-PIM itself made a quiet public debut before Hot Chips at FMS 2026 in Santa Clara earlier in July, where it won the FMS Best of Show Award. Hot Chips 2026 was where Samsung published the architecture details, operational modes, and measured silicon results that make independent evaluation possible. The Herald Business reported the FMS Best of Show recognition alongside the Hot Chips benchmarks.
Does AI Compute Belong Inside the Memory Chip?
The argument against PIM-in-mobile is not performance — the benchmark data is clear. The structural concern that the memory industry’s Hot Chips week surfaced is adoption mechanics. The same week Samsung presented LPDDR5X-PIM, d-Matrix demonstrated a 3D-DRAM inference accelerator at 100 terabytes per second by fusing logic directly atop DRAM dies, and Micron published data showing the memory wall will compound through 2038 regardless of HBM generation. Multiple architectural bets are being placed simultaneously: HBM for cloud, 3D-DRAM for high-throughput inference racks, LP-PIM for mobile and edge.
Samsung’s PIM approach asks a different question from d-Matrix’s and from HBM’s: not “how do we build a faster dedicated memory for AI?” but “how do we add AI compute to the memory that already exists in every device, without making anyone change their board?” The 561-ball package answer to that question is either Samsung’s masterstroke or its principal constraint. If the answer to “can we build AI compute into mobile memory?” is yes — and Hot Chips silicon says it is — the next question is whether device makers will trust the accuracy, the SDK, and the supply chain enough to design LPDDR5X-PIM into products shipping in 2027 and 2028.
GAIA and its HP and Lenovo validation are the most visible current answer to that question.
Frequently Asked QuestionsWhat is processing-in-memory, and why does putting it in LPDDR5X matter?
Processing-in-memory embeds small compute units — specifically multiply-accumulate engines — directly inside a memory chip’s banks, so that the chip can perform arithmetic on the data it stores rather than waiting for a processor to fetch that data for calculation. Prior PIM implementations were confined to High Bandwidth Memory, which is expensive, power-hungry, and unsuitable for mobile or edge devices. LPDDR5X is the low-power DRAM standard in virtually every smartphone and laptop. Moving PIM to LPDDR5X means the same inference-acceleration capability that existed only in data-center AI hardware can now reach devices people carry and carry prices OEMs can absorb.
How is Samsung LPDDR5X-PIM different from High Bandwidth Memory?
HBM stacks multiple DRAM dies vertically and connects them to an AI accelerator through a silicon interposer, delivering very high bandwidth but consuming roughly three times the silicon area of conventional DRAM per gigabyte, requiring specialized packaging, and costing far more per unit. LPDDR5X-PIM uses the same physical package as standard LPDDR5X — the same 561-ball array that is already in every modern smartphone and AI PC design — and achieves 614 GB/s of effective PIM bandwidth not through a wider bus but by eliminating most data movement between memory and processor. HBM4 delivers up to 2 terabytes per second per stack and remains faster; LPDDR5X-PIM costs and fits where HBM cannot go.
Will LPDDR5X-PIM come to smartphones?
Samsung has not announced a smartphone product roadmap for LPDDR5X-PIM. The more immediate commercialization path is through GAIA, Samsung’s 4nm AI PC companion accelerator being developed by its System LSI division, for which prototype chips have reportedly been delivered to HP and Lenovo for performance validation, with mass production targeted for as early as 2027. A smartphone deployment would likely follow a successful AI PC rollout and may depend on LPDDR6-PIM standardization via JEDEC, which Samsung hopes to initiate before the end of 2026.
Is there a catch to the triple-speed benchmark?
Two known limitations. First, an output accuracy gap: Samsung acknowledged at Hot Chips 2026 that LPDDR5X-PIM results differ slightly from standard LPDDR5X outputs, and said optimization work is ongoing. The company has not quantified the gap publicly, and said it expects performance gains to hold as accuracy improves. Second, the 3.01× token throughput figure was measured on Samsung’s own edge AI accelerator SoC running Llama 3.1 8B — not on third-party hardware. Real-world results on other platforms with JEDEC-standard controllers may vary, and large-scale independent benchmarks are not yet available for a chip in working-silicon validation rather than mass production.