TSMC to Keep Microbump for HBM Packaging for Now, Tasks Suppliers with 5μm Challenge — BigGo Finance

Taiwan’s TSMC has decided to maintain its existing microbump approach for the foreseeable future in advanced packaging that connects high-bandwidth memory (HBM) to AI accelerators, and has requested that materials and equipment partners develop finer 5-micrometer (μm) bonding technology, according to industry sources. A transition to hybrid bonding is now expected only after the late fourth generation or early fifth generation of HBM.

According to materials industry sources on September 2, TSMC has ordered partners to develop 5μm-class bumps and the underfill materials to support them. The request calls for making the microbumps currently used in advanced packaging even lower and finer. South Korean and Japanese supply chains have already begun development, with mass production of 5μm-class bumps estimated for the second half of 2027.

Current bump heights are 15–25μm for HBM3E and approximately 10μm for HBM4. Japanese materials suppliers have previously stated that quality assurance is difficult below 15μm, and 5μm falls well below that assurance threshold.

The reason bumps must be lowered comes down to HBM cube height limits and interconnect density. Under JEDEC (Joint Electron Device Engineering Council) specifications, HBM cube height is capped at 775μm. With input/output contact counts continuing to rise while the height ceiling cannot be exceeded, the bumps themselves must be made lower and denser.

TSMC’s CoWoS advanced packaging attaches HBM—already stacked by GPU and memory vendors—onto a silicon interposer using microbumps. While SK Hynix and Samsung Electronics perform the 16-layer stacking internally within the HBM, as accelerator-side contacts increase, the bumps placed on CoWoS must also be lowered accordingly.

HBM’s first and second generations used relatively large solder bumps, but microbumps became the mainstream around the third generation as layer counts and I/O expanded. SK Hynix has adopted the MR-MUF approach, which applies liquid underfill after mass reflow, while Samsung Electronics uses TC-NCF, which inserts a film-type underfill and applies thermocompression bonding.

Hybrid bonding, which had been discussed as the next-generation technology, eliminates bumps entirely and directly bonds copper pads. While it enables thinner and denser connections, TSMC already uses this technology for logic chip stacking (SoIC) but continues to adhere to microbumps for attaching HBM to the interposer. The company is reluctant to abandon a proven approach in terms of yield, inspection, and mass production.

The bonding technologies adopted by TSMC and the two memory makers are summarized below.

CompanyBonding TechnologyApplication ProcessCharacteristicsTSMCCoWoS (microbump)GPU-HBM interposer bondingMaintains proven, high-yield approachTSMCSoIC (hybrid bonding)Logic chip stackingDirect copper pad bonding without bumpsSK HynixMR-MUFHBM die stackingStrong against thin-die warpage, but high thermal resistance and narrow gap-fill marginSamsung ElectronicsTC-NCFHBM die stackingExcellent productivity and heat dissipation, but sensitive to chip warpage

Note: The contrasting characteristics of MR-MUF and TC-NCF are based on a summary by IT media outlet ServeTheHome, which covered SK Hynix’s presentation at Hot Chips 2026 on-site.

A 5μm-class bump is a highly challenging task requiring void-free underfill, residual flux control, and bonding alignment to be achieved simultaneously. This is why TSMC is understood to have distributed development across multiple materials and equipment partners.

The direction within the HBM stack is consistent. At Hot Chips 2026 last month, SK Hynix presented a roadmap to maintain microbump-based MR-MUF without adopting hybrid bonding through HBM4 and HBM4E. Direct bonding has been deferred to HBM5 and beyond 20-layer stacking. Analysts note that JEDEC’s decision to raise the stack height limit from 720μm to 775μm provided headroom for this extension.

JEDEC officially announced the JESD270-4 HBM4 standard in April last year, confirming the 775μm ceiling. The HBM4 specifications SK Hynix disclosed at Hot Chips 2026 target more than 20,000 TSVs and 16,148 base microbumps within the 775μm height limit, aiming for over 2TB/s of bandwidth and more than 40% improvement in power efficiency. The 12-layer stack is already in mass production, while the 16-layer stack is in the qualification stage. The 48GB-class HBM3E 16-layer product is also reported to have reduced chip thickness, interlayer spacing, and bump pitch by nearly half to fit two additional layers within the same height limit as the existing 12-layer stack.

A materials industry source said, “TSMC’s microbump development request can be interpreted as an intention to go with lower microbumps rather than direct bonding this cycle,” adding, “Development of sub-15μm bumps already exists but assurance remains difficult; the key challenge is developing the underfill that can guarantee them, more so than the bumps themselves.”

Meanwhile, at Semicon Taiwan 2026 held the same day, SK Hynix presented custom HBM with compute functionality embedded in the HBM4 base die as its next-generation AI memory technology. Kim Ho-sik, SK Hynix vice president and head of memory system research, explained that reducing the process of moving data to the GPU for processing could improve large language model (LLM) inference performance by up to 5.15 times.

SK Hynix manufactured base dies with its own technology through HBM3E, but from HBM4 onward it will leverage TSMC’s advanced logic process. Logic processes are better suited for integrating more complex circuits and functions than conventional memory processes. The two companies are jointly developing HBM4 base dies and next-generation packaging technology.

Packaging structures are also evolving to reduce data movement. In the current 2.5D structure, GPU and HBM are placed side by side on an interposer to exchange data, consuming approximately 2–3 picojoules (pJ) per bit. In future 3D structures, DRAM will be stacked directly on neural processing units (NPUs) to reduce travel distance and power consumption, potentially lowering energy use to 0.2–0.3pJ per bit.

The following chart illustrates the difference in per-bit energy consumption between the 2.5D structure and the projected 3D structure.

▲ Median values of the per-bit energy consumption ranges disclosed by SK Hynix (2.5D structure: 2–3pJ, 3D structure: 0.2–0.3pJ). Actual figures may vary depending on system configuration, and the 3D structure is a pre-commercialization projection.

China’s CXMT is also drawing attention as a fast follower. CXMT has reportedly begun small-volume HBM3E production. Alibaba-affiliated T-Head and AI chipmaker Cambricon are testing CXMT’s HBM3E in their own processors. CXMT raised CNY 57.9 billion (approximately $8.6 billion) through its Shanghai stock exchange listing in July and plans to deploy the funds toward expanding production capacity.

Tech Times assessed CXMT’s small-volume HBM3E production as an example of the limits of Washington’s semiconductor export controls against China, introduced in October 2022 and strengthened in December 2024 to target HBM. However, as shown below, the technology gap between CXMT and leading players remains intact, leading to the interpretation that while the controls did not narrow the gap itself, they did play a role in delaying entry timing.

The technology gap remains substantial. SK Hynix began HBM3E mass production in March 2024, roughly two and a half years ahead of CXMT. Samsung Electronics and SK Hynix are currently mass-producing HBM4, a full generation ahead. Samsung Electronics supplied 3.6TB/s-class HBM4E 12-layer samples to key customers on May 29, while SK Hynix supplied HBM4E 12-layer samples in June. Industry observers estimate CXMT’s HBM technology lags leading players by three to five years.

The following table summarizes packaging technology changes by HBM generation.

CategoryHBM3EHBM4HBM4E and BeyondBump Height15–25μm~10μm5μm (development target)Bonding MethodMicrobumpMicrobumpMicrobump → hybrid bonding transition under reviewUnderfillMR-MUF / TC-NCFMR-MUF / TC-NCFNew void-free underfill required

Note: Mass production of the 5μm-class bumps requested by TSMC from partners is estimated for the second half of 2027.

TSMC’s decision is expected to have significant implications across the HBM supply chain. With the hybrid bonding transition delayed, materials and equipment suppliers face the challenge of pushing existing microbump technology further. The 5μm-class bump, in particular, exceeds the range that Japanese materials suppliers have said is difficult to quality-assure, making underfill material development a key variable.

At the same time, HBM demand continues to grow. As AI’s center of gravity shifts from training to inference, data movement volumes are surging, driving greater requirements for HBM capacity and bandwidth. SK Hynix estimates that tokens generated in multi-agent environments could increase by up to 15 times compared to existing workloads. If 1,000 agents using 32K context operate simultaneously, KV cache alone would require approximately 10.5 terabytes (TB)—roughly half the total HBM capacity of an Nvidia Vera Rubin NVL72 system.

As the pace of packaging technology evolution is directly tied to HBM supply capability, analysts note that TSMC’s decision to maintain microbumps improves supply stability in the short term but could constrain performance improvement in the medium to long term by delaying the hybrid bonding transition. With HBM market competition and technology roadmaps intertwined, collaboration among materials, equipment, memory, and foundry players is becoming increasingly critical.