Conceptual diagram of the iHBM solution unveiled by SK hynix. SK hynix
SK hynix (000660.KS) has unveiled a new high-bandwidth memory (HBM) technology that dramatically addresses the heat dissipation issue, the biggest challenge for artificial intelligence (AI) semiconductors. The new technology, dubbed “iHBM,” embeds cooling elements inside the package to overcome the structural limitations of HBM, whose performance degrades due to heat generated during astronomical computational processes. SK Group Chairman Tae-won Choi will leverage the new technology to meet Nvidia CEO Jensen Huang again early next month to strengthen their HBM alliance.
SK hynix on Wednesday unveiled the “iHBM” technology, which incorporates an “Integrated Cooling Element (ICE)” inside the HBM package. The ICE serves as a kind of “cooling tower” that uses silicon material with high thermal conductivity to discharge heat generated internally to the outside. The iHBM places the ICE at the bottom-most “die-to-die physical layer (D2D PHY),” where heat is concentrated, forming a separate heat dissipation path. This reduces thermal resistance by more than 30% compared to existing HBM, enabling stable operating characteristics even in high-temperature, high-load environments.
Nvidia’s next-generation AI accelerator, Rubin Ultra, boasts computing performance of approximately 100 quadrillion operations per second, or 100 petaFLOPS. In this process, power consumption of up to 230 kilowatts (kW) per rack is expected. This is approximately 64% more than the current Blackwell GPU (up to 140 kW per rack). Nvidia has also unveiled development plans for “Feynman,” the successor to Rubin Ultra. For existing HBM to support Feynman’s performance, the heat dissipation issue arising from computational processes must be resolved. SK hynix has presented iHBM as the solution.
The industry has assessed iHBM as a technology that resolves the chronic heat dissipation issue without going against existing design flows. Choi Jae-hyuk, professor at Seoul National University’s Graduate School of Convergence Science and Technology, said, “AI semiconductors have evolved by widening data pathways (D2D PHY) to reduce signal loss between the internal system-on-chip (SoC) and memory (HBM).” He added, “In this process, empty space remains at the top, and the idea of erecting a cooling pillar there to dissipate heat is an excellent attempt.”
SK hynix plans to secure mass production capability by utilizing existing verified packaging processes. The application of iHBM technology will make the HBM manufacturing process more complex. To address this, SK hynix plans to manufacture iHBM using the wafer-level packaging (WLP) process based on “Mass Reflow Molded Underfill (MR-MUF)” applied to existing products.
In this case, a mass production system can be established immediately without introducing new equipment, securing stable production and yield. Using the existing process also enhances compatibility with customers’ existing system-in-package (SiP) designs, allowing big tech customers to apply iHBM immediately without design modifications.
SK hynix plans to introduce iHBM starting with the 8th-generation HBM (HBM5). This is to meet the demanding requirements of next-generation graphics processing units (GPUs) from its key customer Nvidia. Chairman Choi plans to meet CEO Huang at “GTC Taipei 2026,” held in conjunction with Computex in Taipei, Taiwan, on the 1st of next month, to closely discuss AI chip and HBM technology advancements. Chairman Choi is also expected to meet TSMC Chairman C.C. Wei to strengthen the trilateral alliance among SK hynix, Nvidia, and TSMC.