The agreement includes the development of a comprehensive portfolio of memory and interface IP, alongside extended certification of Cadence’s design and analysis tools. These tools incorporate AI-driven capabilities across digital, custom and 3D integrated circuit (3D‑IC) design, providing a platform intended to support increasingly complex systems used in artificial intelligence (AI) and high-performance computing (HPC).
The companies said the collaboration aims to deliver a “signoff-ready” design environment, allowing chipmakers to move more efficiently from development to production. The platform is expected to support applications ranging from data centre infrastructure to edge computing and intelligent devices.
The new agreement builds on work announced in 2025, when Cadence tools and IP were certified for use across multiple Samsung Foundry manufacturing nodes, including its 2nm technology. The latest expansion adds further design resources, including support for high-speed interconnects such as NVIDIA’s NVLink-C2C and GPU-accelerated software libraries. It also includes IP for widely used standards such as PCIe, UCIe and advanced memory interfaces.
Boyd Phelps, senior vice-president and general manager of Cadence’s Silicon Solutions Group, said the growing demands of AI systems were driving the need for more advanced chip design solutions. “AI infrastructure and physical AI are pushing the industry into advanced node and 3D‑IC designs that demand far more capacity, integration and signoff confidence than ever before,” he said. “With this next phase of our Samsung Foundry collaboration, we’re giving joint customers a production‑proven platform to deliver the next-generation of AI and HPC systems to market faster.”
Samsung Foundry said the expanded partnership reflects increasing demand for advanced semiconductor manufacturing technologies. Jongshin Shin, executive vice-president and head of Foundry Design Platform Development at Samsung Electronics, said: “Customers are increasingly drawn to Samsung Foundry’s second-generation 2nm for leading-edge AI designs that must keep pace with the exploding demand across AI infrastructure and emerging physical AI applications. Our expanded Cadence partnership delivers a robust semiconductor and 3D-IC platform with advanced Memory, Interface IP and AI-optimised flows for superior performance, efficiency and innovation.”
As part of the collaboration, Cadence is providing a range of certified design tools for the 2nm process. These include its Innovus Implementation System for digital chip design, Virtuoso Studio for analogue and custom work, and the Integrity 3D‑IC platform for multi-chip system integration. Additional tools handle power analysis, timing verification and final “signoff” checks before manufacturing.
The companies are also supporting Samsung’s 3D Cube-H technology, which uses hybrid copper bonding to stack chips vertically, enabling improved performance and more efficient use of space. The combined design flow incorporates planning, routing, verification and optimisation tools to manage the added complexity of 3D‑IC architectures.
Nvidia is among the technology partners working within this ecosystem. The company is using Cadence tools on Samsung’s 2nm platform to develop high-bandwidth interconnects and GPU-accelerated systems. Timothy Costa, vice-president and general manager of computational engineering at Nvidia, said: “As AI workloads scale and system architectures grow more demanding, the semiconductor ecosystem depends on tools and platforms that can keep pace with simulation and design complexity at advanced nodes. By leveraging Cadence’s GPU-accelerated design flows on Samsung Foundry’s second-generation 2nm platform, we’re optimising the performance and delivery of next-generation AI architectures and high-bandwidth interconnects.”
The expanded partnership reflects broader industry trends, as chipmakers seek to address rising demand for advanced processing power in AI applications. As designs become more complex and manufacturing nodes shrink, collaboration between design software providers and semiconductor manufacturers is becoming increasingly important to ensure performance, efficiency and reliability in next-generation devices.