The chips that power artificial intelligence will stay critically short until at least 2030 — and every company in the world building AI infrastructure needs to plan around that number right now.

That was the central message from Computex 2026’s second day in Taipei on Tuesday, where SK Group Chairman Chey Tae-won repeated his warning that the global supply gap for high-bandwidth memory will persist through the end of the decade, then announced his company would double its total wafer production capacity within five years. Hours later, Nvidia CEO Jensen Huang walked to the SK Hynix booth on the Computex exhibition floor, picked up a marker, and wrote “Please Make More” on an HBM4E wafer on display. The world’s largest AI chip designer was publicly asking its top memory supplier to move faster — and the supplier’s chairman had just said he needed until 2030.

That exchange, buyer and seller in the same building on the same afternoon, was the sharpest summary of where AI infrastructure stands: demand so intense that the CEO of the world’s most valuable company is writing notes to a supplier, and a shortage so structural that doubling capacity still does not close the gap.

Why High-Bandwidth Memory Architecture Makes the Shortage Structurally Permanent

To understand why building more fabs does not solve the problem quickly, it helps to understand what HBM actually is.

High-bandwidth memory is not conventional DRAM placed faster on a circuit board. It is a three-dimensional stack of DRAM dies connected vertically through microscopic copper pathways called through-silicon vias, then bonded to a GPU or AI accelerator on a silicon interposer — a thin substrate that acts as a high-speed bridge between processor and memory. Where standard DDR5 memory ships data at roughly 50 to 100 gigabytes per second, a single HBM3E stack delivers up to 1.2 terabytes per second. That is not an incremental improvement; it is the difference between a two-lane road and an eighteen-lane expressway, and it is why Nvidia’s AI accelerators cannot function at design speed without HBM sitting adjacent to the compute die.

The packaging process that fuses these components — TSMC’s Chip-on-Wafer-on-Substrate, known as CoWoS — is one of only a handful of manufacturing bottlenecks that could single-handedly slow global AI progress. CoWoS places the GPU logic die and HBM stacks side by side on the silicon interposer with interconnect densities that conventional organic substrates cannot support. Without CoWoS, an Nvidia Blackwell or Vera Rubin chip is a collection of dies, not a deployable AI accelerator. TSMC has been expanding CoWoS capacity from roughly 35,000 wafer starts per month in late 2024 toward a projected 120,000 to 130,000 per month by the end of 2026 — a roughly fourfold increase in under two years — and demand still outpaces it.

The deeper structural problem is wafer economics. Micron disclosed in earnings materials that producing one unit of HBM3E consumes approximately three times the wafer capacity required to produce the same number of bits in DDR5. TrendForce puts the ratio even higher: one gigabyte of HBM requires the equivalent of four gigabytes of standard DRAM in wafer area. Every wafer diverted to HBM production is a wafer that can no longer produce consumer memory for laptops, smartphones, or enterprise servers. That diversion is rational — revenue per wafer for HBM runs three to five times higher than for conventional DDR5 — but it creates a cascading shortage that ripples from AI data centers down to anyone buying a device with DRAM inside.

Chey acknowledged the timeline bluntly on the Computex floor. “AI actually wants to have a lot of HBM, and once you make the HBM, we have to use a lot of wafers,” he told reporters. A greenfield fab, he added, takes more than five years to build from scratch — placing even an immediate construction start near the tail end of the shortage window his own forecast describes. Wafer supply is running more than 20 percent below demand industry-wide, according to figures Chey has cited repeatedly, and the three companies that dominate the market — SK Hynix, Samsung, and Micron — currently supply only about half of the medium-to-long-term memory demand that global hyperscalers and AI chip designers actually require.

“This is no longer a cyclical imbalance. It is a structural reallocation of the memory market driven by AI infrastructure economics,” said Sanchit Vir Gogia, chief analyst and CEO at Greyhound Research. Shrish Pant, director analyst at Gartner, confirmed that HBM wafer reallocation is “very real and is definitely impacting the market till the end of 2027,” while noting that meaningful price relief is unlikely to arrive before late 2027 even under optimistic scenarios.

Goldman Sachs responded to the Computex announcements by lifting its 2028 operating profit forecasts for SK Hynix by 24 percent and for Samsung Electronics by 23 percent, treating the confirmed shortage extension as a structural tailwind for both companies’ earnings through the remainder of the decade.

Samsung’s HBM5 Reveals Where Memory Competition Goes Next

Tuesday’s most technically significant hardware moment came not from SK Hynix but from its rival. Samsung Electronics unveiled the first physical mockup of HBM5 — the eighth generation of high-bandwidth memory — on the Computex floor, disclosing two architectural advances that indicate where the performance ceiling for AI memory now sits.

The first is process. Samsung plans to manufacture HBM5’s base die — the logic layer at the bottom of the stack that handles communication with the host processor — on its in-house 2-nanometer foundry process, a step down from the 4-nanometer node used in HBM4 and HBM4E. The tighter process node improves power efficiency and processing throughput in the base die, reducing the heat generated per operation at the most thermally critical layer of the stack.

The second is thermal management. As HBM stacks grow taller — HBM5 is being prepared in 12-layer, 16-layer, and 20-layer configurations — heat accumulation between dies becomes the binding engineering constraint, not interconnect density. Samsung’s new HPB (Heat Path Block) structure embeds proprietary copper thermal-dissipation pathways directly within the HBM package, extracting heat from the core and base dies and directing it to a heat spreader at the top of the package. SK Hynix announced its own competing thermal architecture, iHBM, one week earlier, claiming a 30 percent reduction in thermal resistance — and now both companies are racing to solve the same heat bottleneck.

Samsung mass production of HBM5 is planned for around 2028, following HBM4E volume ramp. The competitive dynamic at Computex was difficult to misread: Samsung’s CTO Song Jai-hyuk briefed reporters at the same show where Nvidia CEO Jensen Huang spent visible time at the SK Hynix booth endorsing that supplier’s products. The market share picture reflects this: SK Hynix held approximately 57 percent of global HBM revenue as of the third quarter of 2025, according to Counterpoint Research, with Samsung at around 22 percent and Micron at 21 percent. TrendForce’s more recent estimates suggest Samsung’s 2026 share is rising toward 28 percent as its HBM4 qualification with Nvidia’s systems progresses.

How Does Agentic AI Change Memory Demand Through 2030?

Qualcomm CEO Cristiano Amon opened Computex 2026 a day earlier with a declaration: “2026 is the year of agents.” The claim carried specific quantitative weight. Amon told the audience that global AI token consumption currently runs at 31.7 billion tokens every ten seconds. By 2030, he projected, that figure will reach 1.27 trillion tokens in the same ten-second window: a roughly fortyfold increase.

The engineering significance of that projection connects directly to the HBM shortage. Every AI inference token requires compute and memory bandwidth. A conversational AI agent completing a simple query needs around 10,000 tokens per task. A background agentic AI completing a multi-step workflow — booking travel, reconciling financial data, managing a software deployment — requires around one million tokens for a single operation. As agent workloads migrate from human-speed conversation to machine-speed background execution, the demand curve does not smooth out across the day; it runs continuously, around the clock.

“Agents, unlike humans, don’t sleep,” Arm CEO Rene Haas said at the show — a sentence that encapsulates the fundamental demand difference between the AI era and every prior computing cycle. When every device on a network is running agents continuously rather than only when a human is actively using it, the baseline memory and compute floor becomes dramatically higher. The global AI agent ecosystem is now tracking toward roughly $2 trillion in projected 2026 spending across hardware, software, and services, according to Qualcomm’s projections — positioning Computex 2026 as the event where the magnitude of that demand met the hard engineering limits on supplying it.

Qualcomm’s strategic response to this demand picture was announced at the same keynote: a new data-center product brand called Dragonfly, marking the company’s first entry into AI server infrastructure. The move signals that Qualcomm believes the compute demand generated by agentic AI on edge devices — 6 billion phones, 2 billion PCs, 2 billion wearables, half a billion vehicles — cannot be routed entirely through hyperscale cloud infrastructure. The edge-to-cloud routing problem becomes a primary cost and latency challenge when token volumes scale fortyfold in four years.

Market Records Reflect Decade-Scale Bets on AI Infrastructure

For investors, Computex 2026 has completed a revaluation of the semiconductor sector that would have seemed implausible five years ago. Taiwan’s benchmark TAIEX index closed at a record 45,557 points on Tuesday, driven by AI investment momentum and easing geopolitical risk expectations; by Wednesday morning it had surged further past 46,500. Nvidia, now the world’s most valuable company at approximately $5.4 trillion in market capitalization, arrived at the show after CEO Jensen Huang had already spent more than a week in Taipei working through CoWoS advanced-packaging constraints with TSMC Chairman C.C. Wei.

SK Hynix crossed $1 trillion in market capitalization for the first time last week, joining Samsung and Micron in a group whose combined valuation reflects the market’s conviction that AI infrastructure demand will compound through the remainder of the decade. Goldman Sachs’s revised profit forecasts — up 24 percent for SK Hynix and 23 percent for Samsung by 2028 — treated the confirmed shortage extension not as a risk but as a structural earnings driver.

Huang framed the supply situation with characteristic precision: his company had secured supply for “very robust growth” across CPU and GPU systems, while acknowledging in the same breath that demand continues to run ahead of what can be produced.

Geopolitical pressure has not disappeared from the equation. The show unfolded against ongoing Chinese military pressure around Taiwan, and the export status of Nvidia’s highest-end Blackwell and Vera Rubin accelerators to China remains restricted — a condition Huang described candidly by saying Nvidia has “largely conceded” the high-performance China market to domestic rival Huawei. A partial clearance allowing H200 chip sales to roughly ten Chinese companies was announced by the Trump administration in May 2026, though no deliveries have occurred as the transaction remains in regulatory limbo. Huang, pressed on the risk of a Taiwan crisis, offered the semiconductor industry’s most honest assessment of the scenario: “Everybody’s supply chain should be as diversified… as possible, so that we can have resilience.”

Physical AI Arrives on the Computex Floor

The fifth and most visually striking development at Computex 2026 was the emergence of physical AI as a mainstream hardware category. Nvidia debuted the Isaac GR00T Reference Humanoid Robot — an open platform built on a Unitree H2 Plus chassis — at GTC Taipei, combining 75 degrees of freedom — 31 across the body and 22 per hand — with an Nvidia Jetson AGX Thor T5000 compute module running the Isaac GR00T foundation model. The robot is deliberately non-proprietary: Stanford University, ETH Zurich, UC San Diego, and Ai2 have already committed to use the platform for general-purpose physical intelligence research. Commercial availability from Unitree is scheduled for late 2026.

The compute at the robot’s core — the Jetson Thor T5000 — is built on Nvidia’s Blackwell GPU architecture, delivering up to 2,070 FP4 trillion operations per second with 128 gigabytes of memory: meaningful AI inference power in a form factor designed to move through a human workspace at human scale.

Qualcomm similarly unveiled a robotics reference design under its Dragonfly brand, and a dedicated AI Robotics Zone opened for the first time in the Taipei World Trade Center’s TWTC Hall 1, drawing sustained crowds throughout the day.

“The era of physical AI is approaching,” Huang said at a Computex press conference. Memory, agents, stock markets, supply chains, and robots are not separate stories at this year’s show. They are different faces of a single structural shift: AI has become the primary driver of what hardware gets built, where it gets made, and who controls the economics of it through the end of the decade. For infrastructure planners, investors, and enterprise buyers, the most important number from Computex 2026 is not a market cap or a benchmark score — it is 2030, the earliest credible date at which the memory bottleneck that constrains every AI system on earth begins to ease.

Frequently Asked Questions

How long will the AI memory shortage last?

SK Group Chairman Chey Tae-won stated at Computex 2026 that the global shortage of high-bandwidth memory chips will persist through at least 2030, driven by AI systems that require far more wafer capacity per chip than conventional DRAM. Gartner analyst Shrish Pant confirmed that meaningful price relief is unlikely before late 2027, while Greyhound Research described the situation as a structural reallocation of the global memory market rather than a temporary supply cycle.

What is high-bandwidth memory and why does AI need it?

High-bandwidth memory is a three-dimensional stack of DRAM dies connected vertically through through-silicon vias, then bonded alongside a GPU or AI accelerator on a silicon interposer. A single HBM3E stack delivers up to 1.2 terabytes per second of bandwidth, compared to roughly 50 to 100 gigabytes per second for standard DDR5. AI training and inference workloads stream enormous volumes of model data continuously, and only HBM delivers the bandwidth density needed to keep high-end accelerators from sitting idle waiting for data.

Why does building more memory fabs not fix the shortage quickly?

Constructing a greenfield memory fabrication facility takes more than five years from groundbreaking to volume production, according to Chey. In addition, HBM requires roughly three to four times the wafer area per unit of memory output compared to standard DRAM — meaning that even expanding total wafer capacity does not linearly expand HBM output. CoWoS advanced packaging at TSMC, the final assembly step that bonds HBM to GPU dies, is also operating near capacity despite a roughly fourfold expansion since late 2024.

How does the AI agent economy affect memory demand?

Qualcomm CEO Cristiano Amon projected at Computex 2026 that global AI token consumption will grow from 31.7 billion tokens per ten seconds today to 1.27 trillion tokens per ten seconds by 2030 — a roughly fortyfold increase — driven primarily by agentic AI systems that run continuously rather than responding only to human queries. Because agentic workloads require up to one million tokens per task versus roughly ten thousand for simple conversational AI, the shift to agents multiplies memory bandwidth demand by orders of magnitude beyond what current data center capacity was designed to handle.