The agreement adds memory and interface IP, including SerDes, PCIe, UCIe and NVLink-C2C support for AI and HPC designs.

Cadence and Samsung Foundry have announced development of a portfolio of memory and interface IP and expanded certification of Cadence digital, custom, 3D IC and system design and analysis flows for Samsung Foundry’s second-generation 2nm process. The work is intended to support AI infrastructure and related designs for data center, edge and intelligent device applications.

The announcement follows the companies’ 2025 certification of Cadence tools and IP on multiple Samsung Foundry process nodes, including second-generation 2nm. Under a new multi-year agreement, the Cadence portfolio will be expanded to include additional memory and interface IP, including NVLink-C2C-enabled interconnect and CUDA-X GPU-accelerated libraries, spanning high-speed SerDes, PCIe, UCIe and memory interfaces for second-generation 2nm. The agreement also expands certified Cadence flows for AI, HPC and advanced system designs.

Design and 3D IC flows for second-generation 2nm

Cadence and Samsung Foundry said they now offer a certified flow for second-generation 2nm that includes the Cadence Innovus Implementation System for digital implementation, Virtuoso Studio for analog and custom design, Integrity 3D IC Platform for 3D IC planning and implementation, Voltus IC Power Integrity Solution for power integrity and system-level power analysis and Quantus Extraction Solution and Tempus Timing Solution for signoff.

Cadence said the flow supports second-generation 2nm design features including glitch power optimization in the place-and-route flow using the Innovus system and Genus Synthesis Solution, as well as a hierarchical flow for performance, power, area and turnaround time targets.

Samsung 3D Cube-H design is supported with a planning, implementation and signoff flow for hybrid copper bonding technology, including Cadence Cerebrus Intelligent Chip Explorer, Integrity 3D IC, Innovus Implementation, Voltus IC Power Integrity and Pegasus Verification System. The flow includes silicon interposer auto-routing and optimization, with Tempus and Pegasus used for signoff and verification.

NVLink-C2C interconnect support

NVIDIA is using the Cadence and Samsung Foundry platform for advanced-node and 3D IC development to support NVLink-C2C interconnect and CUDA-X GPU-accelerated capabilities for accelerated computing systems and AI semiconductor development.

Edge AI platform work with Ambarella

Ambarella is developing a second-generation 2nm edge AI platform for AI perception and physical AI SoCs used in edge systems including robotics, drones, autonomous machines and sensing applications.

Cadence and Samsung Foundry said they will highlight the partnership and design enablement work during the Samsung Advanced Foundry Ecosystem 2026 event, including technical sessions and demonstrations focused on second-generation 2nm and 3D IC design flows for GPU-accelerated AI workloads.

For more information, visit cadence.com.