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A modern AI chip is no longer simply a single piece of silicon. It is a densely packed system of compute chiplets, HBM, I/O dies, networking components, and power delivery. Anyone who cannot reliably bring these building blocks together may still fabricate excellent transistors, but in the end all that remains is an expensive pile of individual parts. Intel is responding to this with an organizational restructuring of its foundry division. On June 18, 2026, the company appointed former SK hynix and SK On CEO Seok-Hee Lee as Executive Vice President of Intel Foundry. Lee reports directly to CEO Lip-Bu Tan and takes over leadership of Advanced Packaging, system integration, back-end technology development, and back-end manufacturing. Intel now describes Advanced Packaging as a focused business unit with its own leadership. The company is thus separating work on chip manufacturing processes more clearly from the later connection, assembly, and testing of the individual dies.
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Front-End and Back-End are being more clearly separated
The front-end essentially comprises actual wafer fabrication: transistors, interconnect layers, and process nodes such as Intel 18A or Intel 14A. This area remains under the leadership of Naga Chandrasekaran. Seok-Hee Lee, by contrast, takes over the downstream steps. These include die singulation, connecting multiple chiplets, integrating memory and networking components, the finished package, as well as parts of testing and volume production.
The two areas remain part of Intel Foundry. Intel is therefore not establishing a separate packaging company. Rather, the new structure is intended to ensure that the increasingly complex package development receives clearer accountability and its own scaling strategy. Seok-Hee Lee was previously president and CEO of SK hynix and most recently head of battery manufacturer SK On. He also previously worked at Intel and, according to the company, has experience in process development, manufacturing, and building large production organizations. His memory background is particularly interesting for Intel. In AI and HPC systems, logic chips and HBM must work ever more closely together. The electrical connection, power delivery, and cooling of memory are now just as important as the actual GPU or CPU. According to Intel, Lee is expected to help couple logic, memory, networking components, and other chiplets more tightly within a package. In particular, the company is preparing the packaging technologies EMIB-T and HBI for higher production volumes. This is not a minor personnel change. Intel is bringing in a manager who knows the perspective of a major memory manufacturer, precisely into the area where memory and logic will increasingly converge technically. Intel’s EMIB technology connects multiple chiplets via small silicon bridges embedded in the package substrate. Unlike a large silicon interposer, the entire area beneath the chips is not fabricated from silicon. This can reduce material and manufacturing costs. EMIB-T extends this concept with through-silicon vias, or TSVs. These vertical connections run through the silicon bridge and can transport power or signals along a shorter path to the chiplets above. This is particularly relevant for large AI packages with multiple HBM stacks. In such packages, not only must an enormous amount of data be moved, but power delivery must also remain stable and with as little loss as possible despite the growing package area.
Intel cites the following goals for EMIB-T, among others:
According to Intel, current EMIB-T concepts can enable packages with a total area of more than six times that of a single exposure mask. The company wants to increase this scale to more than eight times in 2026 and to more than twelve times by 2028. These are the manufacturer’s target values. What will be decisive is at what yield, thermal robustness, and unit volume such packages can actually be produced. The second key technology is HBI, Intel’s Hybrid Bonding Interface. Here, two dies are coupled directly through very fine copper-to-copper connections. Compared with conventional micro solder bumps, the contact pitches can be significantly smaller. This enables more connections per area, higher bandwidth, and lower energy consumption per transmitted bit. Intel uses HBI, among other things, for Foveros Direct 3D, in which chiplets are stacked vertically on an active base die. Such an arrangement can place logic layers, cache, I/O, or other functions directly on top of one another. EMIB-T and HBI therefore serve different purposes. EMIB-T connects multiple components side by side, while HBI enables particularly tight vertical connections. Intel can also combine both approaches to build so-called 3.5D systems from horizontally and vertically integrated chiplets. Conventional foundry thinking often focuses on the smallest process node. For large AI accelerators, that is no longer sufficient. No manufacturer can economically produce arbitrarily large chips as a single defect-free die. Instead, compute units are distributed across multiple chiplets. In addition, there are HBM, networking chips, and different I/O components, some of which are manufactured on other process nodes. The finished system can therefore contain chips from different manufacturers and fabrication generations. The foundry must not only produce or source each individual die, but also ensure that the entire package functions. The yield of the system depends on every chiplet, every connection, and every assembly step. This is precisely why TSMC, Samsung, and Intel are investing heavily in advanced packaging. Intel is trying to position itself with EMIB, Foveros, and HBI as an alternative for customers who need not only wafer fabrication, but complete system integration. The new leadership structure still says nothing about which external customers will use EMIB-T or HBI in high volumes. Intel names neither order volumes nor specific product names. The capacity of back-end manufacturing is also not quantified in the current announcement. It therefore remains open when EMIB-T and HBI will actually be available in large volumes for external foundry customers. However, Lee’s appointment shows that Intel no longer views this area as a mere add-on to wafer fabrication. Packaging is intended to become an independent selling point and may also attract customers who have their logic chips manufactured partly by other foundries.
Conclusion
With the new structure, Intel is making it clear that foundry competition no longer ends at the wafer edge. Anyone seeking to win AI and HPC customers must be able to connect compute chips, HBM, I/O, and networking components into a functioning overall system. Seok-Hee Lee’s experience at SK hynix therefore fits the task unusually well. Whether he will actually bring EMIB-T and HBI to high volumes remains to be seen, however. Intel has interesting technologies, but it must still prove that it can manufacture them reliably, predictably, and economically for external customers. The personnel decision is therefore not a victory, but a sensible step. Intel appears to have understood that a modern foundry customer does not buy only a process node. In the end, they buy a complete package — and understandably want it to work as well.
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