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In the HBM market, the key question is no longer simply who announces the fastest memory. What matters is who can deliver functional samples to NVIDIA, AMD, Google, or other developers of major AI accelerators in time. A datasheet alone still does not fit into any GPU socket. On 18 June 2026, SK hynix began shipping samples of its new 12-layer HBM4E to major customers. According to the manufacturer, the memory achieves up to 16 Gbit/s per pin, offers 48 GB of capacity per stack, and is intended to deliver energy efficiency more than 20 percent better than the previous HBM4 generation. For SK hynix, this marks the start of customer qualification for a memory generation that is expected to be used in upcoming AI accelerators from 2027 onward. The company does not name the recipients. SK hynix has also not yet announced a production release or a binding date for the start of volume production.
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48 GB in twelve stacked DRAM dies
The new HBM4E consists of twelve stacked memory layers. With a total capacity of 48 GB, this corresponds to four gigabytes, or 32 gigabits, per DRAM layer. The high capacity is relevant for AI accelerators because large models and extensive context windows increasingly require not only compute performance, but also storage directly on the accelerator. HBM is located in the immediate vicinity of the GPU or the custom AI chip and offers a much wider interface than conventional DDR or GDDR memory.
SK hynix specifies a maximum transfer rate of 16 Gbit/s per data lane for HBM4E. The actual total bandwidth of a finished accelerator module depends on the interface width, the number of HBM stacks used, and the memory controller of the respective processor.
The figures come from SK hynix and have not yet been confirmed by independent product tests. In the case of HBM samples, the initial question is whether the memory works reliably in combination with a specific accelerator, reaches the required speed, and can operate within the intended thermal limits. For the twelve layers, SK hynix uses an advanced variant of its MR-MUF packaging technology. In Mass Reflow Molded Underfill, a liquid protective material is introduced between the individual dies after stacking and then cured. The material mechanically stabilizes the stack and is also intended to improve heat transfer. According to SK hynix, thermal resistance has been reduced by 17 percent compared with HBM4. This point is becoming more important with each HBM generation. Higher data rates increase power consumption, while more memory layers make it more difficult to remove heat from the interior of the stack. At the same time, several HBM packages sit very close to an AI processor that can itself draw several hundred watts. An HBM stack therefore cannot be evaluated based on bandwidth and capacity alone. Temperature distribution, material stress, signal quality, and long-term reliability are equally decisive. Memory that reaches its maximum data rate only for a short time or under exceptionally elaborate cooling would be of little appeal for large AI data centers. SK hynix is not the first manufacturer to ship HBM4E samples. Samsung had already announced on 29 May 2026 that it was shipping its own 12-layer HBM4E samples to global customers. Samsung also specifies up to 16 Gbit/s per pin, along with improvements in energy efficiency and thermal behavior. Samsung鈥檚 lead in timing is therefore approximately three weeks. However, this does not yet indicate a later market victory. Samples must first pass the often months-long qualification procedures of chip developers. These tests include signal stability, thermal behavior, yield, package integration, and reliability under continuous load. SK hynix has a strong position in existing HBM generations and is regarded as NVIDIA鈥檚 most important HBM partner. At the beginning of June 2026, the two companies also announced a multi-year collaboration on memory technologies for future AI platforms. For that very reason, the HBM4E shipment is relevant. SK hynix must show that it can maintain its existing market position despite Samsung鈥檚 earlier sampling. At the same time, Micron is pushing into the same market with its own HBM roadmaps. With HBM4 and HBM4E, the role of the so-called base die is also changing. This lowest logic chip connects the stacked DRAM layers to the AI accelerator and handles parts of data transfer and control.
The more complex this logic becomes, the more memory products can be customized for individual customers. Future HBM variants may therefore differ not only in capacity and speed, but also in interfaces, internal functions, and cooperation with a specific accelerator. That increases development effort. At the same time, it binds memory manufacturers and chip developers more closely together. An HBM stack thus becomes less of an interchangeable standard component and more of a jointly developed part of the overall AI processor. SK hynix has so far provided no details on whether the HBM4E samples shipped now already use customer-specific base dies or initially correspond to a more general reference configuration. Shipping the samples is an important milestone, but not yet proof of successful mass production. Customers must first evaluate the components with their own processors, interposers, packages, and cooling systems. The production yield, available quantities, and whether 16 Gbit/s can be sustained under real-world conditions remain open questions. It is also still unclear which upcoming accelerators will actually use HBM4E. SK hynix merely says that it is working closely with key customers and preparing for timely mass production. There is still no specific quarter or named initial customer.
Conclusion
With its 48-GB HBM4E, SK hynix is delivering precisely what upcoming AI accelerators need technically: more capacity, higher data rates, and improved thermal behavior. However, the decisive phase starts only now. Samples are patient; customer qualification is far less so. Samsung was a few weeks faster in shipping, while SK hynix brings its strong existing position and its close NVIDIA partnership to the table. Which supplier ultimately receives the largest orders will be decided not by a press release, but by yield, reliability, and the ability to deliver millions of complex memory stacks on time. In the HBM market, what matters now is not only who runs first, but who can also make it through volume production at full speed.
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