Samsung Electronics (005930) and SK Hynix (000660) are transitioning to mass production this year to seize the initiative in the Compute Express Link (CXL) market, which is rapidly emerging as the next-generation AI memory standard following high-bandwidth memory (HBM). Both companies are applying the latest CXL 3.2 communication specification to their new products to maximize performance, while also accelerating the development of architectural technologies that go beyond simple capacity expansion to organically integrate with existing memory hierarchies.
According to industry sources on the 19th, Samsung Electronics recently applied CXL 3.2 technology to its new memory product, the “CXL Memory Module (CMM-D) 3.0,” which targets mass production by year-end. The product was originally developed based on CXL 3.1, but the company’s strategy is to boost performance by upgrading to the latest version just before production begins. The key feature of CXL 3.2 is the first-time introduction of the “CXL Hot-Page Monitoring Unit (CHMU),” which monitors data usage frequency and optimizes data flow across multiple memory devices. Samsung Electronics previously unveiled the CXL 1.1-based CMM-D 1.0 in 2022 and the CXL 2.0-based CMM-D 2.0 in 2023. The CMM-D 3.0 is expected to be the industry’s first product to enter mass production.
SK Hynix is also preparing to mass-produce an equivalent product. While the company has not disclosed a specific production timeline, it began customer sales efforts last month at the international exhibition “HPED 2026,” where it first showcased samples of its “2nd Generation CMM-DDR5” featuring CXL 3.2. SK Hynix first unveiled its CXL 2.0-based first-generation product in 2024. Both companies’ new products aim to roughly double bandwidth compared to their predecessors to actively address the surging demand for AI memory. Micron is also reportedly accelerating internal development of next-generation products based on CXL 3.1 or 3.2, following the 2023 unveiling of its CXL 2.0 memory “CZ120.”
The fundamental reason CXL is gaining attention as a next-generation memory standard lies in the physical capacity limitations of HBM and Double Data Rate (DDR) memory, which currently process AI data. HBM and DDR are directly connected to graphics processing units (GPUs) and central processing units (CPUs), respectively, meaning that adding more memory requires first increasing the number of GPUs and CPUs themselves, causing costs to rise exponentially. In contrast, CXL memory forms a separate memory tier distinct from HBM and DDR. Even without a direct connection to GPUs or CPUs, it can assist computation with latency measured in hundreds of nanoseconds via the CXL interface, often described as a “data highway.” This enables memory capacity expansion at relatively low cost.
Beyond product launches, both companies are focusing on developing architectures that combine CXL with existing memory tiers to maximize synergies. SK Hynix recently unveiled its “Inference Memory Tier Expansion (IMTE)” architecture to the academic community. Current AI memory systems follow an “HBM → DDR → Solid-State Drive (SSD)” structure. The new architecture adds “CXL Hybrid Memory” with capacities ranging from several to tens of terabytes, expanding the hierarchy to “HBM → DDR → CXL Memory → SSD.” In this architecture, CXL memory goes beyond simple capacity expansion to serve as a hub that predicts the hot data needed by HBM and DDR, pre-fetching it from SSDs and delivering it in advance. SK Hynix explained that this approach improved AI inference efficiency by 35.7% compared to existing systems.
Samsung Electronics also emphasized its optimization expertise in a CXL technology white paper released on the 9th of this month, noting that its CXL 2.0 memory (CMM-D 2.0) can achieve AI inference performance approaching 92% of the latest DDR5 products. Additionally, similar to SK Hynix’s hybrid memory, Samsung is developing “CMM-Hybrid (H),” which applies CXL not only to DRAM but also to NAND flash.
The movement toward CXL memory commercialization is also evident in the actions of global Big Tech companies. Major players including Nvidia, Intel, and AMD are responding to the paradigm shift by supporting CXL memory compatibility in their next-generation chips slated for release in the second half of this year. Microsoft launched a pilot cloud service late last year that incorporates CXL memory to improve server efficiency, marking the first such deployment.
This competition is seen as an inevitable consequence of the explosion in AI data. Global investment bank Goldman Sachs projects that worldwide monthly AI token usage will surge 24-fold from 5 quadrillion tokens this year to 12 quadrillion tokens by 2030. Considering that each token typically occupies 4 bytes of capacity, the memory required for AI chips to run the latest large language models (LLMs) has already ballooned to tens of terabytes.
“Although CXL memory is still in the early stages of commercialization, suppliers are preemptively developing technology and preparing for competition because customers could demand it at any time, much like HBM,” an industry insider said. In a related context, High-Bandwidth Flash (HBF), which vertically stacks NAND to simultaneously achieve high capacity and high bandwidth, is also being actively developed as a candidate for a new memory tier. SK Hynix, in particular, anticipates a significant increase in demand around 2030 and is pursuing technology standardization in partnership with SanDisk. Nvidia also plans to introduce “Compute Memory Expansion (CMX),” a new NAND-based memory tier, in its upcoming “Vera Rubin” lineup.