Samsung Electronics is making an aggressive move to strengthen its leadership in the next-generation high-bandwidth memory (HBM) market by introducing its advanced 2-nanometer GAA (Gate-All-Around) process into its eighth-generation HBM5. The strategy aims to boost power efficiency and increase data processing speeds by more than 50% compared to the previous generation.

Koo Ja-heum, Executive Vice President and head of technology development at Samsung Electronics’ foundry business, stated in an interview with the company’s semiconductor newsroom on July 27, “HBM5 is expected to require an improvement in operating speed of approximately 50% or more over the previous generation, HBM4E.” He added, “To meet industry demands, we will apply the 2nm process using a GAA structure to the HBM5 base die and implement higher-density TSV (Through-Silicon Via) technology.”

The base die is a critical component that acts as a high-speed interface, shuttling data between external processors — such as GPUs (Graphics Processing Units) or CPUs (Central Processing Units) — and multiple layers of DRAM. As HBM evolves through successive generations, demands for higher performance and power efficiency intensify. Samsung’s strategy with this 2nm process adoption is to raise the technological bar for the next-generation AI semiconductor market.

Samsung has previously applied its 4nm fourth-generation process to the base dies of HBM4 and HBM4E, achieving data processing speeds of 14 Gbps (gigabits per second). Starting with HBM5, the company intends to apply the 2nm GAA process to dramatically improve both performance and power efficiency. GAA is a next-generation transistor architecture where the gate surrounds all four sides of the current channel, enabling more precise current control. It can simultaneously enhance performance and power efficiency compared to the existing FinFET structure.

Koo highlighted Samsung’s “turnkey” production system — which integrates memory, foundry, and packaging — as a core competitive advantage. “HBM is a product built by stacking core dies and a base die together in a package,” he explained. “By manufacturing the HBM core die in our memory division and the base die in our foundry, then packaging them in our backend process, we can shorten the time required to complete mass production while also being highly advantageous from a cost perspective.” He noted that optimizing factors such as data transfer speeds, thermal management, and yield from the design stage can significantly reduce development timelines.

Samsung also expressed confidence in its leading-edge foundry competitiveness on the same day. “Following the world’s first mass production of a 3nm process applying GAA technology, we began mass production of our first-generation 2nm process in the second half of last year,” Koo said. “In the second half of this year, we plan to begin mass production of new mobile products based on our second-generation 2nm process, which features improved yield and performance.”

Orders from major customers are expanding on the back of this leading-edge process technology. “Starting with the order for Tesla’s 2nm product last year, we have continued to receive orders from numerous large customers,” Koo said. “Demand is being driven by the application of our 4nm process to the HBM4 base die and a new LPU (Language Processing Unit) product from a U.S. AI company.” Samsung’s customer base is rapidly broadening beyond mobile clients to include CSPs (Cloud Service Providers) and AI/HPC (High-Performance Computing) companies.

Meanwhile, Samsung Electronics is solidifying its position in the AI memory market by supplying its HBM4 for AMD’s cutting-edge rack-scale infrastructure platform, “Helios,” and the MI455X accelerator. The MI455X accelerator, recently unveiled by AMD in San Francisco, utilizes TSMC’s 2nm and 3nm chiplet technology, with Samsung’s HBM4 serving as the core memory. A single Helios rack integrates 31 terabytes of HBM4 memory, with initial shipments scheduled to begin at the end of the third quarter and volume production ramping up in the fourth quarter of this year.

Samsung plans to expand its application areas beyond AI and HPC into automotive and robotics. The company will also continue to pursue the development of next-generation semiconductor technologies, including silicon photonics for data centers and CPO (Co-Packaged Optics). “Samsung Foundry plans to continue expanding its market share based on the solid technological competitiveness of its leading-edge processes,” Koo emphasized.

Samsung Electronics Foundry Process Roadmap by HBM Generation

GenerationProduct NameBase Die ProcessData Processing Speed6th GenHBM4 / HBM4E4nm 4th Gen (FinFET)14 Gbps7th GenHBM4E (Next)Enhanced 4nm ProcessUp to 16 Gbps8th GenHBM52nm GAATarget: 50%+ improvement over predecessor

Source: Compiled from Samsung Electronics Semiconductor Newsroom interview and AMD Helios platform announcement materials