Song Jae-hyuk, Chief Technology Officer of Samsung Electronics’ Device Solutions (DS) Division, unveiled HBM5 technology for the first time at a press briefing held at Samsung Display’s booth during “Computex Taipei 2026,” Asia’s largest IT exhibition, which opened on the 2nd at the Nangang Exhibition Center in Taipei, Taiwan. Reporter Kim Yun-su
Samsung Electronics (005930.KS) has unveiled its next-generation high-bandwidth memory (HBM) 5 technology, which it plans to supply to Big Tech firms including Nvidia. With memory demand surging amid Big Tech’s race for artificial intelligence (AI) chips, Samsung’s strategy is to seize supply leadership through technological superiority based on the most advanced processes.
Song Jai-hyuk, chief technology officer (CTO) of Samsung Electronics’ Device Solutions (DS) division, held a press briefing at the Samsung Display booth at “Computex Taipei 2026,” Asia’s largest information technology (IT) exhibition, which opened Tuesday at Nangang Exhibition Center in Taipei, Taiwan. “We will continue to strengthen our next-generation memory technology competitiveness with HBM5, which applies a 2-nanometer (nm, one-billionth of a meter) base die process and Heat Path Block (HPB) for the first time,” he said. He also unveiled a mockup of HBM5 for the first time.
Song stressed that HBM5 can dramatically improve performance over HBM4E in areas such as bandwidth, operating speed and heat control. The base die, the bottom layer of HBM, plays the role of seamlessly connecting the upper DRAM layer, known as the core die, with logic dies such as graphics processing units (GPUs). Samsung Electronics’ HBM base die is manufactured by the company’s foundry business division. Currently, a 4-nm process has been applied to this year’s HBM4 and next year’s HBM4E. SK hynix uses TSMC’s 12-nm process.
Asked about concerns that maintaining chip yield and stability becomes more difficult at advanced process nodes, Song expressed confidence, saying, “As an integrated device manufacturer (IDM), Samsung Electronics is optimizing through comprehensive solution competitiveness spanning memory, foundry, logic and packaging.”
HPB will also be applied to HBM5 for the first time. HPB is a design technology that enhances heat control performance by creating a new pathway to draw heat generated in HBM to the outside. Recently, SK hynix also unveiled a similar iHBM technology. “HPB has already been implemented and verified through HBM4E,” Song stressed. “This means reliability and stability have been comprehensively verified.”
HBM5 is being prepared for release as standard products with 12, 16 and 20 stacks of DRAM. While the mass production timeline was not disclosed, it is expected to be in 2028, following next year’s HBM4E. “We are also developing the 1d DRAM process (after the current 1c), which will likely be applied starting with HBM5E,” Song said.
Samsung Electronics also displayed an actual HBM4E unit, which it recently shipped as samples for the first time in the world.