![\"aerial](\"https:\/\/www.europesays.com\/korea\/wp-content\/uploads\/2026\/08\/aerial-picture-shows-south-korean-electronics-giant.jpg\")
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This aerial picture shows South Korean electronics giant Samsung’s factory in Vietnam’s Bac Ninh province on June 11, 2024.
\nNHAC NGUYEN\/AFP via Getty Images<\/p>\n
Samsung Electronics is reportedly weighing the relocation of general-purpose DRAM and NAND flash packaging and testing operations from its Cheonan and Onyang backend facilities in South Korea to Vietnam, a move that would free floor space and specialized equipment lines at both sites for the high-bandwidth memory stacking work that is now the company’s most urgent manufacturing priority. Digitimes, citing Korean industry outlet DealSite, reported the consideration on August 14, 2026. Samsung has not publicly confirmed the plan.<\/p>\n
The consideration, reported Friday by Digitimes citing Korean industry outlet DealSite, arrives as Samsung pursues a 47% HBM wafer output increase<\/a> \u2014 from 170,000 wafers to roughly 250,000 wafers per month by the end of 2026 \u2014 with a production yield on its sixth-generation HBM4 product that HBM4 yield reached 80 percent<\/a> as of earlier this month, well ahead of the year-end target Samsung had originally set. Sustaining that ramp requires backend throughput to keep pace with front-end wafer output \u2014 and it is there, not in the wafer fabs, where the bottleneck now lives.<\/p>\n Why Cheonan and Onyang Cannot Do Both<\/p>\n The reason Samsung cannot simply run HBM stacking alongside commodity DRAM and NAND packaging on the same floor comes down to process incompatibility that no floor-space optimization can resolve.<\/p>\n Manufacturing a conventional DRAM or NAND package involves roughly 700 process steps: die sawing, wire bonding or flip-chip attachment, molding, and electrical test. Manufacturing an HBM stack requires approximately 19 additional materials engineering steps<\/a> that use entirely different equipment. Those additional steps include through-silicon via (TSV) formation \u2014 etching and copper-filling microscopic vertical channels through each memory die \u2014 followed by wafer thinning that reduces each die from standard wafer thickness to approximately 30 micrometers (0.0012 inches), precision die stacking, and thermal compression bonding (TCB), a process that bonds 12 to 16 thinned dies into a single tower at controlled temperature and pressure. None of the equipment for any of these steps can also perform conventional DRAM or NAND packaging operations, as the HBM stacking and packaging architecture<\/a> is fundamentally different from standard assembly.<\/p>\n Samsung confirmed in a TrendForce-reported briefing earlier this year that its Cheonan at full HBM stacking capacity<\/a> across its C1, C2, and C3 production lines. The site has no room to expand HBM stacking operations without removing or replacing the commodity packaging equipment that currently occupies the same cleanroom floor space. Onyang has more total area \u2014 Samsung broke ground on a new eight-floor HBM backend building<\/a> there in early 2026, a structure designed specifically for HBM stacking with TSV-based process lines \u2014 but that building’s HBM lines also cannot share floor space with commodity packaging.<\/p>\n What the Digitimes\/DealSite report describes is the solution to that constraint: move the commodity packaging and testing work out to Vietnam entirely, freeing the Korean sites to be dedicated HBM backend hubs. Industry sources describe it as a “dual-track” packaging strategy \u2014 advanced personnel from Cheonan transferred to Onyang’s new HBM facility, while general DRAM packaging from Onyang moves to Vietnam.<\/p>\n Vietnam Has Been Building Samsung’s Backend Infrastructure for Years<\/p>\n The reported consideration builds on infrastructure Samsung has been expanding in Vietnam for decades. The group operates six Vietnam manufacturing facilities<\/a>, one R&D center, and one sales entity across four locations in northern and southern Vietnam: Bac Ninh, Thai Nguyen, Hanoi, and Ho Chi Minh City. Samsung is already Samsung’s largest foreign investment in Vietnam<\/a>, with total committed investment exceeding $23 billion across multiple facilities.<\/p>\n Most recently, Samsung filed a proposal with Vietnamese authorities to build a semiconductor test plant in Thai Nguyen Province in northern Vietnam \u2014 its first dedicated chip testing facility in the country \u2014 at a cost of 39 trillion Vietnamese dong (approximately $1.49 billion USD at the August 15, 2026 exchange rate of 1 USD \u2248 26,178 VND). Construction began at an industrial park approximately 60 kilometers (37 miles) north of Hanoi in early 2026, with operations scheduled to begin in November 2027. That plant, focused on legacy DRAM and NAND flash test work, is projected to validate up to 153.3 billion gigabits DRAM annually<\/a> and 255.6 billion gigabits of NAND annually.<\/p>\n Vietnam has become a significant hub for semiconductor backend operations more broadly. Intel, Amkor Technology, and Hana Micron all operate backend plants in the country, providing an established ecosystem of skilled labor, regulatory familiarity, and supplier infrastructure for assembly, packaging, and testing work \u2014 precisely the type of operations Samsung would be routing there.<\/p>\n What Is HBM and Why Does It Demand Its Own Dedicated Lines<\/p>\n High-bandwidth memory is the architecture that makes frontier AI possible at scale. Where conventional DDR5 memory communicates with a processor across a bus 64 bits wide, HBM4 \u2014 Samsung’s current generation \u2014 communicates across a 2,048-bit bus HBM4 architecture<\/a>, delivering a minimum of 2 terabytes per second of memory bandwidth per stack. That bandwidth \u2014 delivered by a stack of 12 DRAM dies connected through thousands of TSVs and placed directly adjacent to a GPU on a silicon interposer \u2014 is what allows large language models and multimodal AI systems to sustain computation at the speeds frontier training and inference require.<\/p>\n HBM demand growing 70 percent annually<\/a> and is expected to account for roughly 25% of total DRAM wafer production in 2026. Because each HBM wafer consumes approximately three to four times the resources<\/a> of a conventional DRAM wafer \u2014 due to the additional TSV and stacking steps \u2014 every wafer redirected to HBM removes the equivalent of three to four commodity DRAM units from supply. That trade-off is deliberate: HBM commands substantially higher margins than commodity memory, and it cannot be substituted in AI accelerator designs.<\/p>\n Samsung’s HBM4, which entered mass production in February 2026, delivers a consistent data rate of 11.7 Gbps<\/a> per pin \u2014 exceeding the 8 gigabits per second industry standard required for Vera Rubin AI accelerator compatibility. On June 5, 2026, Nvidia CEO Jensen Huang confirmed all three suppliers<\/a> in Seoul \u2014 Samsung, SK Hynix, and Micron \u2014 had completed qualification to supply HBM4 for Vera Rubin, the first time all three major memory vendors had simultaneously received public certification for the same platform.<\/p>\n Supply-chain analysts estimated SK Hynix held 60 to 70 percent HBM4 volume<\/a> of Vera Rubin allocations, with Samsung supplying approximately 25 to 30% and Micron the remainder. Closing that gap requires Samsung to convert more wafer output into shippable, qualified HBM stacks \u2014 which requires more backend throughput.<\/p>\n How Samsung and SK Hynix Split Global HBM Supply<\/p>\n Samsung and SK Hynix control 90 percent of HBM<\/a> production globally. The decisions each company makes about where its backend capacity points will shape the pace at which AI accelerator supply grows \u2014 and, by extension, how quickly AI infrastructure investment can scale from current levels.<\/p>\n Samsung’s HBM4 yield had climbed from below 60 percent<\/a> at mass production launch in February to approximately 80% as of August 10, 2026, according to Seoul Economic Daily reporting that cited industry sources. That yield progress, driven in part by improvements in the thermal compression non-conductive film bonding process, positions Samsung to compete more effectively for HBM volume share in the second half of 2026 and into 2027. Samsung also began shipping the first HBM4E samples shipped May 29<\/a> \u2014 the generation after HBM4, with a data rate of 16 gigabits per second and bandwidth of 3.6 terabytes per second per stack \u2014 to major customers on May 29, 2026.<\/p>\n To support front-end output that can feed more backend stacking, Samsung is expanding 1c DRAM to 200,000 wafers<\/a> (10-nanometer sixth-generation) monthly capacity by end-2026, primarily through the Pyeongtaek P4 facility expansion and conversion of existing lines. Samsung’s P5 facility in Pyeongtaek is expected to be operational around 2028. SK Hynix M15X HBM4 production 2027<\/a> is expected to begin by mid-2027.<\/p>\n What the Backend Relocation Would Mean for AI Memory Supply<\/p>\n If Samsung proceeds with the Cheonan and Onyang backend relocation, the implications extend beyond Samsung’s own production numbers. The AI accelerator supply chain’s pace depends not on how many wafers Samsung can produce \u2014 front-end wafer fab expansion is already underway at Pyeongtaek P4 \u2014 but on how quickly those wafers can be stacked, bonded, tested, and shipped as finished HBM modules. Backend throughput is the final constraint, and it is currently the tightest link in the chain.<\/p>\n