SK Hynix has laid out concrete milestones for its next-generation high-bandwidth memory (HBM) roadmap. The 12-hi HBM4 product has entered mass production, while the 16-hi version is undergoing customer qualification. For ultra-high stacking of 20 layers or more, the company is positioning hybrid bonding as the core technology, moving away from conventional approaches to strengthen its packaging competitiveness.<\/p>\n
On August 24 (local time), at the Hot Chips 2026 semiconductor conference held at Stanford University, Lee Jae-sik, vice president of packaging engineering at SK Hynix America, delivered a presentation titled “Advanced Packaging for HBM.” He stated that the 12-hi HBM4 product is in normal mass production and that the 16-hi version has progressed to the customer qualification stage.<\/p>\n
The announcement directly rebuts various rumors that have dogged SK Hynix. Late last year, speculation circulated that problems had emerged with HBM4 products, forcing a redesign from scratch. There were also reports that Nvidia had raised the performance bar for HBM4 to be used in its next-generation Rubin GPU from 8\u201310 Gbps to 11 Gbps, delaying certification.<\/p>\n
However, Jensen Huang, CEO of Nvidia, dismissed those rumors in June during a Q&A with Korean reporters, saying, “All three companies\u2014Samsung Electronics, SK Hynix, and Micron\u2014have passed HBM4 qualification testing.” SK Hynix also said on its second-quarter conference call that “HBM4 began volume shipments to major customers in the second quarter, with yields and quality approaching levels of the previous-generation HBM3E product.”<\/p>\n
This presentation marks the first time the status of the 16-hi product has been concretely specified. SK Hynix unveiled a 16-hi prototype at CES 2026 earlier this year, saying that “development of the production version is progressing smoothly in line with customer schedules.” The company has now officially confirmed that the product has entered the qualification phase.<\/p>\n
Rival Samsung Electronics is pursuing a different strategy. In its fourth-quarter 2025 earnings call in January, Samsung said, “Customer demand for the 16-hi HBM4 product is very limited, and considering the planned sampling of HBM4E 12-hi at the same capacity this year, we judge that commercializing 16-hi mass production is unnecessary.” The company added, however, that “we have already secured technology capable of mass-producing 16-hi packages, so there will be no issue responding to changes in customer requirements.”<\/p>\n
Packaging Becomes the Core of HBM Competition<\/p>\n
In his presentation, Lee emphasized that the axis of HBM competition is shifting from memory performance itself to packaging technology. “Going forward, we need to look not only at HBM itself but also at how the customer’s packaging technology affects HBM,” he said. “As we enter the era of 3D stacking, this will no longer be a problem for HBM makers alone\u2014it will become a challenge that must be developed jointly with foundries.”<\/p>\n
This reflects a fundamental shift in how AI semiconductors are developed. In the past, memory was completed first and then installed into PCs or servers. But AI semiconductors package the GPU and HBM together on a silicon interposer, functioning as a single chip. This requires memory makers, GPU designers, foundries, and packaging firms to co-design from the outset.<\/p>\n
Another distinguishing feature is that HBM is mounted first in the AI semiconductor assembly process, unlike conventional memory. “In the past, memory went into the final stage of system assembly, but AI HBM is mounted first on the interposer,” Lee explained. “Because it must withstand all the heat and mechanical stress generated in subsequent processes, reliability has become far more important.”<\/p>\n
Preparing for 20-Hi and Beyond with Hybrid Bonding<\/p>\n
SK Hynix identified hybrid bonding as the key technology for stacking HBM beyond 16 layers to 20 layers or more. Currently, HBM primarily uses MR-MUF (mass reflow-molded underfill), which connects DRAM chips with fine bumps and fills the empty spaces. But as stack counts rise, individual DRAM chips must be made thinner, and the burden of simultaneously addressing chip warpage and heat dissipation grows.<\/p>\n
Hybrid bonding is a technology that directly bonds chips together instead of using bumps. Applying this approach allows individual DRAM dies to remain thicker at the same stack height while reducing bump pitch to below 18 micrometers. According to Lee, core die thickness can be increased by up to 24%, and thermal transfer efficiency improves, which is expected to reduce heat issues.<\/p>\n
The company also unveiled technology to address localized hot spots within HBM. “As HBM input\/output speeds increase, heat concentration in certain areas becomes more severe,” Lee said. “To address this, we are developing ‘iHBM’ technology that adds high-thermal-conductivity materials.” Rather than cooling the entire device, the approach targets only the hot spots where heat concentrates.<\/p>\n
Lee also outlined two key areas SK Hynix is focusing on for future HBM performance improvements. “One is expanding data I\/O and increasing per-I\/O speed to widen bandwidth, and the other is improving power efficiency through more TSVs in the logic die,” he explained.<\/p>\n
“HBM bandwidth and capacity will continue to grow, but heat, power, and packaging will become bigger challenges,” Lee said. “The era has begun where these are no longer problems a memory maker can solve alone\u2014customers, foundries, and packaging firms must optimize together.”<\/p>\n","protected":false},"excerpt":{"rendered":"SK Hynix has laid out concrete milestones for its next-generation high-bandwidth memory (HBM) roadmap. The 12-hi HBM4 product…\n","protected":false},"author":2,"featured_media":130060,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[20],"tags":[4287,65849,33220,19854,11825,66308,2295,276,241,275,52225],"class_list":["post-130059","post","type-post","status-publish","format-standard","has-post-thumbnail","category-sk-hynix","tag-hbm4","tag-hot-chips-2026","tag-hybrid-bonding","tag-ihbm","tag-jensen-huang","tag-lee-jae-sik","tag-nvidia","tag-samsung-electronics","tag-sk","tag-sk-hynix","tag-tsv"],"_links":{"self":[{"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/posts\/130059","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/comments?post=130059"}],"version-history":[{"count":0,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/posts\/130059\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/media\/130060"}],"wp:attachment":[{"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/media?parent=130059"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/categories?post=130059"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.europesays.com\/korea\/wp-json\/wp\/v2\/tags?post=130059"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}