{"id":33681,"date":"2026-05-28T19:09:13","date_gmt":"2026-05-28T19:09:13","guid":{"rendered":"https:\/\/www.europesays.com\/korea\/33681\/"},"modified":"2026-05-28T19:09:13","modified_gmt":"2026-05-28T19:09:13","slug":"5-takeaways-from-samsung-foundrys-design-tie-up-with-synopsys","status":"publish","type":"post","link":"https:\/\/www.europesays.com\/korea\/33681\/","title":{"rendered":"5 takeaways from Samsung Foundry\u2019s design tie-up with Synopsys"},"content":{"rendered":"

A fundamentally new approach is required to fuse AI-driven automation and multiphysics intelligence across the entire design and manufacturing flow. That was the crux of the keynote by Synopsys\u202fpresident and CEO Sassine Ghazi at the SAFE Forum 2026, held by Samsung Foundry in San Jose, California.<\/p>\n

Ghazi especially mentioned design and technology co-optimization (DTCO) initiatives for synthesis and layout, as well as sign-off, delivering meaningful power, performance, and area (PPA) enhancements. He also talked about the design partnership between Samsung Foundry and Synopsys, which encompasses production-ready, AI-powered EDA tools, certified interface IP, and silicon-based test capabilities.<\/p>\n

Hyung-Ock Kim, VP and head of the Foundry Design Technology Team at Samsung Electronics, echoed similar views, stressing the need for close alignment across design, test, and manufacturing to ensure the success of AI and multi-die designs on advanced nodes.<\/p>\n

He also presented an update on Samsung Foundry\u2019s collaboration with Samsung for production-ready, AI-powered digital and analog flows. \u201cOur continued close collaboration with Synopsys delivers silicon-based, customer-validated solutions that help our customers reduce design integration risk, improve silicon predictability, and move confidently from design to production for their most innovative solutions,\u201d Kim said.<\/p>\n

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Ravi Subramanian, chief product management officer at Synopsys, briefed on AI-powered digital and analog flows for Samsung\u2019s second- and third-generation 2-nm processes. \u201cAs designs become more heterogeneous, customers need production-ready, silicon-proven solutions that address complexity and minimize risk from silicon to systems,\u201d he said. \u201cOur work with Samsung Foundry translates years of DTCO and silicon learning into enablement that helps our customers get their advanced designs to market quickly and with confidence.\u201d<\/p>\n

\"\"<\/p>\n

The partnership encompasses AI-powered EDA flows, multiphysics sign-off, interface IPs, and silicon-based test patters. Source: Synopsys<\/a><\/p>\n

Below are the five key tenets of this design partnership between Samsung Foundry and Synopsys.<\/p>\n

Production-ready digital and analog flows for 2-nm process<\/p>\n

As part of DTCO initiatives, Synopsys Fusion Compiler delivers measurable power and performance improvements in the third-generation 2-nm class process compared to the second-generation 2-nm class process.<\/p>\n

Sign-off with certified multiphysics capabilities<\/p>\n

Synopsys PrimeShield process sensitivity analysis and PVT Explorer support design-specific optimization and engineering change order (ECO) decisions during sign-off. That leads to frequency improvement of up to 2.7% within 5% leakage current degradation. Moreover, Synopsys Totem-SC, a newly certified electromigration (EM) and IR drop analysis solution, improves silicon design power integrity and reliability in second-generation 2-nm and 4-nm class processes.<\/p>\n

3DIC with hybrid copper bonding<\/p>\n

Samsung Foundry and Synopsys have joined hands to enable scalable 3D multi-die designs through certified multiphysics signoff solutions delivered within Synopsys 3DIC Compiler, a unified exploration-to-signoff platform being validated on a hybrid copper bonding (HCB) 3D test chip.<\/p>\n

This platform brings together planning, implementation, and multiphysics analysis to enable co-optimization across integrated compute, memory, and advanced packaging systems for Samsung\u2019s 3DIC solutions with HCB technology. And it replaces manual, margin-based approaches with automated, AI-driven system optimization to accelerate productivity and enhance the quality of results (QoR).<\/p>\n

Interface and foundation IP portfolio<\/p>\n

Synopsys offers a broad portfolio of IPs across Samsung Foundry\u2019s advanced processes, ranging from 14-nm, 8-nm, and 5-nm processes to the latest 4-nm and second-generation 2-nm nodes. The interface IP offerings cover UCIe, PCIe 7.0, 112G\/224G, MIPI, LPDDR6, DDR5 MRDIMM Gen2, and USB4. Likewise, its foundation IPs include embedded memories, logic libraries, GPIOs, security IP, and Silicon Lifecycle Management (SLM).<\/p>\n

AI-powered tests<\/p>\n

Samsung Foundry and Synopsys are also applying silicon-proven methodologies to design-for-test (DFT) and manufacturing test capabilities to reduce test cost and improve test quality for designs on advanced process nodes. Furthermore, physically aware tests and failure diagnosis at the die and multi-die level improve test quality and failure analysis turnaround time with results validated on silicon at Samsung Foundry.<\/p>\n

For instance, Samsung Foundry teams employed Synopsys TestMAX along with AI-assisted automatic test pattern generation (ATPG) technologies to reduce test patterns and test cycles by up to 20%. Samsung Foundry customers leveraging these AI-powered, silicon-based design and manufacturing test capabilities acknowledge test efficiency improvements of up to 20%.<\/p>\n

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