Dutch lithography equipment giant ASML disclosed at the SEMICON Taiwan 2026 Advanced Process Technology Forum that its High-NA EUV lithography systems have officially entered volume production, with cumulative wafer exposures worldwide surpassing 1.35 million wafers and 10 systems currently operating across four customer fabs.

Greet Storms, ASML Senior Vice President and Head of High-NA EUV Product Management, said in her presentation that as global customer demand for advanced lithography capabilities continues to climb, the company has optimized its technology to bring equipment productivity to volume-production standards, laying the foundation for semiconductor process shrinks over the next decade.

Volume Production Data Fully Disclosed

Storms publicly revealed multiple key metrics on High-NA EUV commercialization for the first time. On the installation front, four customers globally have completed installation of 10 High-NA EUV systems and put them into operation, with three additional systems in shipment and installation. Among these, certified EXE:5200B exposure systems have achieved a throughput of 135 wafers per hour in acceptance testing, demonstrating productivity levels capable of supporting high-volume manufacturing.

On system stability, Storms noted that global High-NA EUV tool availability—the proportion of total calendar time during which equipment can be used for actual production—has improved to 84%, is expected to reach 90% by the end of 2026, and continues trending toward a 93% target. This progress stems from ASML applying experience accumulated on the existing NXE platform to EXE systems, strengthening diagnostic capabilities and preventing the same issues from recurring.

On precision performance, the systems have demonstrated excellent matched-machine overlay accuracy and focus capability, establishing a precision foundation for angstrom-level node production.

Intel 18A Process First to Adopt

High-NA EUV technology has achieved a critical milestone. ASML and Intel have both previously announced that the Intel 18A process node, using ASML EXE High-NA EUV technology, has officially entered mass production of Intel’s Core Ultra 3rd-generation series processors codenamed “Panther Lake.” This marks the first application of High-NA EUV in high-volume logic products, signaling the technology’s transition from validation to actual manufacturing.

Storms emphasized that High-NA EUV’s core commercial value lies in replacing multi-patterning with single exposure. Compared to 0.33 NA EUV, which requires complex and costly multi-patterning processes, 0.55 NA High-NA EUV—with its higher resolution—can increase the number of layers using single exposure, directly reducing mask layer counts and defect rates while shortening wafer cycle times and overall costs.

Breakthrough in 2D Chip Design Space

High-NA EUV brings entirely new design possibilities to 2D chip layouts. Thanks to its extremely high resolution and contrast, chip designs can now use single-exposure 2D metal patterning directly, replacing the complex structure that previously required two 1D metal layers plus one via layer. This breakthrough is expected to reduce total metal layer counts, lower resistance and capacitance losses, and increase logic cell density, providing chip design engineers with greater design flexibility and performance headroom.

In DRAM scaling, High-NA EUV’s imaging capability can support technology extension across up to five future 2D DRAM process nodes, from 1C and 1D all the way to 0A, 0B, 0C, and 0D. In advanced logic processes, it can support scaling from the 2nm node continuously down to 0.7nm and 0.5nm nodes.

Regarding High-NA’s half-field exposure limitations and focus control challenges, ASML has proposed mature engineering solutions. Through chip-leveling algorithms, focus correction, and a 148mm wafer clamp design, the expected focus tolerance range can exceed 30nm, maintaining control performance comparable to the NXE platform. For half-field design requirements, ASML provides a 175μm stitching compensation zone to increase design flexibility, flexibly addressing the different design challenges of DRAM and logic chips.

Capacity Roadmap Outlook

ASML has established a stable 0.55 NA EUV technology roadmap spanning more than 10 years. Storms said the company will continue to boost EXE platform capacity, advancing from the EXE:5200B to the next-generation EXE:5400E, by increasing EUV source power (progressively from 600W to 1000W), accelerating wafer and reticle handling speeds, and introducing PEP solutions—with the goal of raising acceptance-test throughput to 180 wafers per hour before the end of this decade.

According to a September 1 report from industry research firm TrendForce, ASML’s capacity roadmap is more specific than previously disclosed: in AB exposure mode, throughput will rise progressively from 135 wafers per hour on the EXE:5200B, to 160 on the EXE:5200C, 175 on the EXE:5200D, and 180 on the EXE:5400E; if switched to AA exposure mode, throughput is expected to exceed 210 wafers per hour. ASML also revealed it is planning a next-generation high-capacity platform codenamed EXE:5600, with a target throughput exceeding 250 wafers per hour, though no specific volume production timeline has been announced.

System GenerationAB Mode Throughput (wafers/hour)StatusEXE:5200B135Certified via acceptance testing; current flagship modelEXE:5200C160On capacity roadmapEXE:5200D175On capacity roadmapEXE:5400E180Target before end of this decadeEXE:5600 (planned)250+No volume production timeline announced

Note: The AA exposure mode throughput target (exceeding 210 wafers per hour) is not tied to a specific system generation; data source same as above.

On tool availability, according to a September 2 report from tech media outlet Bits&Chips, Storms reiterated in her presentation that the current 84% availability rate is one of the final hurdles ASML must clear before meeting customer volume-production requirements. The company is simultaneously reducing both planned downtime and unplanned extended interruptions, while porting diagnostic and maintenance experience from the NXE platform to the EXE platform to raise availability to stable volume-production levels by year-end.

Global Customer Adoption Progress

Beyond Intel’s 18A process, adoption timelines for other foundry and memory majors are gradually emerging. According to TrendForce, citing South Korean media ZDNet and The Elec, SK Hynix introduced its first EXE 5200B system for volume-production R&D at its M16 fab in the second half of 2025, representing an early-stage move toward next-generation DRAM scaling. Samsung Electronics has not yet announced a specific timeline for introducing High-NA EUV in memory products, but plans to adopt the technology on its 1nm-class logic process expected to enter production around 2030.

ASML concluded that the High-NA EUV platform will combine higher resolution, single-exposure imaging, continuously improving productivity, and design flexibility to provide core support for long-term scaling of advanced semiconductor processes worldwide, officially ushering in a new era of semiconductor manufacturing from 2nm to the angstrom generation.