Intel engineers working on an ASML High NA EUV tool in Intel’s Fab 25. – Image: Intel
At this week’s SPIE Photomask Technology + EUV Lithography conference in Monterey, Intel Foundry and ASML presented a status update regarding the commercialization and high-volume manufacturing (HVM) deployment of High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography. The announcement centers on the news that Intel Foundry and ASML have collectively processed over one million 300-mm wafers on the High-NA platform across tool installation, R&D calibration, PDK development, and early HVM production. Intel also confirmed that High-NA EUV (utilizing ASML’s TWINSCAN EXE architecture) is currently deployed on select critical layers for the Core Ultra Series 3 processors, better known as Panther Lake, which are built on the Intel 18A process node.
Under standard Low-NA EUV (NA = 0.33), practical single-exposure resolution bottoms out at roughly 26nm (or 13nm half-pitch). Pushing logic density below 2nm-class nodes on 0.33 NA forces foundries into complex multi-patterning schemes, which drastically increase mask counts, defect density, process complexity, and cycle time. By scaling the projection optics to NA = 0.55, High-NA EUV improves single-exposure resolution down to ~16nm pitch. This gives chipmakers like Intel considerably more headroom for patterning the extremely tight pitches required by sub-2nm-class process technologies while reducing or eliminating multi-patterning.
Intel Foundry’s revelation that High-NA EUV is active on production lines for Panther Lake is an interesting detail about its process integration strategy. Rather than executing a wholesale swap of the entire lithography stack to 0.55 NA, which would be economically and operationally impractical given the extreme cost of EXE-series scanners, Intel is utilizing High-NA opportunistically by applying it exclusively to the tightest-pitch layers where eliminating multiple 0.33-NA exposures can justify the substantially higher operating cost of an EXE scanner.
The insides of these chip fabrication tools are unimaginably complex. – Image: ASML
According to Intel, yield, overlay error budget, defect rate, and scanner availability on these High-NA exposure passes are meeting expectations, with performance matching or exceeding equivalent layers patterned via multi-exposure 0.33-NA NXE platforms. The one million wafer milestone is also notable from a learning-curve perspective; in semiconductor lithography, mature tool status demands extreme mechanical stability, rapid reticle exchange, precise stage acceleration, and tight wafer-to-wafer overlay matching. Amassing one million wafers across R&D and early HVM is substantial proof of the firms’ accumulated operational experience with challenges like source stability, scanner uptime, reticle handling, stage control, and wafer-to-wafer overlay.
Intel’s strategy with High-NA EUV is born out of a calculated risk that requires balancing process complexity versus capital expenditure. By accepting the optical and reticle constraints of 0.55 NA early by installing the first commercial EXE:5000 in 2024 and pushing over one million wafers through the ecosystem ’til now, Intel Foundry appears to have established a process execution lead over foundry competitors like TSMC and Samsung, who have both taken a more conservative approach by prolonging 0.33-NA multi-patterning into their initial 2nm-class generations. Panther Lake yields seem to be strong, and thus appear to validate this High-NA integration on production silicon. Given that, Intel has proved that the primary bottlenecks of 0.55 NA are manageable engineering problems rather than barriers to volume manufacturing.