At the upcoming Leti Innovation Days (LID) World Summit later this month, FAMES programme leaders are scheduled to present \u201coverview and key results highlights\u201d and discuss progress on FD\u2011SOI, embedded memory and RF technologies and updates expected on 10nm FD\u2011SOI pathfinding results; progress towards 7 nm node development; expanded PDK offerings and demonstrators as well as early insights from user projects under the 2026 open-access call.<\/p>\n
The summer period is being described as a checkpoint, where the first wave of user engagement starts to be translated into measurable outputs.<\/p>\n
A major European initiative that\u2019s intended to advance semiconductor innovation and reinforce regional supply chain resilience the FAMES pilot line operates under the coordination of CEA\u2011Leti.<\/p>\n
Earlier this year Neil Tyler, editor of New Electronics, spoke with Jean\u2011Ren\u00e9 Lequepeys, Vice-President and Director of Programs, CEA-Leti, who outlined how the initiative has been designed to provide both advanced technology development and open access infrastructure for industry and research partners across Europe.<\/p>\n
\u201cThe FAMES pilot line is one of five projects launched under the European Chips Act, which aims to boost the region\u2019s semiconductor capabilities and reduce reliance on external supply chains. Bringing together eleven research organisations and universities from across Europe, the programme brings a coordinated approach to next-generation chip technologies. These include partners such as CEA\u2011Leti in France, imec in Belgium, Fraunhofer in Germany and VTT in Finland, among others,\u201d explained Lequepeys.<\/p>\n
The project began in December 2023 and is planned to run over five years, with total funding of \u20ac830 million shared between the European Union and participating member states. Its scope spans several strategic sectors, including automotive, telecommunications, healthcare and data infrastructure.<\/p>\n
Earlier this year saw the formal launch of the pilot line which coincided with the completion of a major expansion at CEA\u2011Leti\u2019s facilities in Grenoble.<\/p>\n
\u201cThe addition of 2,000 square metres of cleanroom space brings the organisation\u2019s total to 14,000 square metres and includes around 80 new semiconductor processing tools,\u201d said Lequepeys. \u201cThese complement an existing base of more than 700 pieces of equipment and are designed to support advanced 300 mm wafer manufacturing. The new facility will serve as a foundation for transferring emerging chip technologies from research into industrial use.\u201d<\/p>\n
Advancing chip architectures<\/strong><\/p>\n A central aim of the FAMES pilot line is to develop a portfolio of technologies that can support new chip architectures with improved performance and lower power consumption. The programme focuses in particular on fully depleted silicon-on-insulator (FD\u2011SOI) technologies at 10 nm and 7 nm nodes, alongside embedded non\u2011volatile memory (eNVM), radiofrequency components, 3D integration techniques and power management technologies.<\/p>\n \u201cThese technologies are intended to enable new approaches to chip design, particularly for mixed-signal applications that combine digital, analogue and RF functions.\u201d<\/p>\n According to Lequepeys, this combination is increasingly important as electronic systems become more complex and interconnected.<\/p>\n The initiative also reflects broader European priorities around sustainability. Alongside technological advancements, the pilot line is designed to promote resource efficiency and support circular manufacturing practices. This includes efforts to minimise waste throughout the semiconductor development process, contributing to wider targets such as the EU\u2019s goal of achieving net-zero emissions by 2050.<\/p>\n \u201cFD\u2011SOI technology plays a key role in the programme\u2019s strategy. Developed and matured within Europe, it is widely regarded as a strong option for balancing power consumption, performance, cost and environmental impact in mixed-signal designs,\u201d Lequepeys explained. \u201cThe technology is already used by major companies including STMicroelectronics and GlobalFoundries and has been adopted in products from a range of global electronics firms.\u201d<\/p>\n Supporting a wide range of applications<\/strong><\/p>\n While the pilot line is rooted in advanced semiconductor processes, its intended applications extend across a broad spectrum of industries. The technologies being developed are expected to support the prototyping of core functions such as sensing, actuation and data transmission, which are fundamental to modern electronic systems.<\/p>\n \u201cPotential use cases include next-generation microcontrollers and processors, chips designed for 5G and 6G communications, smart sensors and imaging systems, as well as edge AI devices and advanced packaging techniques such as chiplets. The project also targets emerging areas such as quantum computing and cryogenic electronics.<\/p>\n \u201cThis \u201cMore than Moore\u201d approach reflects a shift in the semiconductor industry, where innovation is no longer driven solely by shrinking transistor sizes but also by integrating diverse functions into a single system,\u201d according to Lequepeys.<\/p>\n Open access model for industry and research<\/strong><\/p>\n A key feature of the FAMES pilot line is, according to Lequepeys, is its open access model, which aims to make advanced semiconductor capabilities available to a wide range of users. These include academic research groups, start-ups, small and medium-sized enterprises, and larger industrial organisations.<\/p>\n \u201cThe project is structured to provide two main access pathways. In a reactive mode, the consortium assesses requests from users seeking to carry out specific research and development activities. In parallel, a proactive model operates through annual open calls, inviting organisations to apply for access to the pilot line\u2019s tools and technologies,\u201d he explained.<\/p>\n Through these mechanisms, participants can access design kits, modelling tools and experimental platforms to evaluate technologies such as FD\u2011SOI nodes, embedded memory, RF components and 3D integration. The programme also supports multi-project wafer runs, enabling users to test new chip designs in a shared manufacturing environment.<\/p>\n Lequepeys emphasised that this approach is intended to bridge the gap between laboratory research and industrial deployment. By providing access to advanced manufacturing infrastructure, the pilot line enables organisations to move from concept development to functional prototypes and, ultimately, to commercial applications.<\/p>\n Education and skills development<\/strong><\/p>\n In addition to its technological and industrial objectives, the FAMES initiative has a strong focus on training and skills development. The programme includes activities aimed at Master\u2019s and PhD students, providing opportunities to gain expertise in advanced semiconductor technologies.<\/p>\n This emphasis reflects concerns across Europe about the availability of skilled talent in the semiconductor sector. By integrating education into the pilot line\u2019s activities, the project aims to support the development of a workforce capable of sustaining long-term growth in the industry.<\/p>\n Position within Europe\u2019s semiconductor ecosystem<\/strong><\/p>\n \u201cFAMES is designed to complement existing capabilities within Europe\u2019s semiconductor landscape, building on established strengths in areas such as FD\u2011SOI technology and mixed-signal design. It targets markets where Europe already has a strong position, including automotive electronics, industrial systems and communications infrastructure,\u201d said Lequepeys.<\/p>\n \u201cThe pilot line also forms part of a broader network of initiatives under the Chips Act. These include other pilot lines focused on areas such as nanoelectronics, wide bandgap materials and photonics. CEA\u2011Leti is involved in all five programmes, linking FAMES to a wider ecosystem of research and development activities.\u201d<\/p>\n In addition, the project is connected to competence centres and collaborative programmes supported by the Chips Joint Undertaking, helping to align research efforts with industrial needs across the continent.<\/p>\n Strengthening long-term competitiveness<\/strong><\/p>\n The establishment of the FAMES pilot line reflects a wider effort to enhance Europe\u2019s long-term competitiveness in semiconductor technology. By combining advanced research, industrial collaboration and open access infrastructure, the initiative aims to accelerate innovation while reducing barriers to entry for smaller organisations.<\/p>\n Lequepeys highlighted the importance of continuing to develop FD\u2011SOI technology in particular, noting its advantages in terms of power efficiency and system integration. When combined with embedded memories, RF components and 3D integration techniques, it enables new approaches to chip design that can support future applications across multiple sectors.<\/p>\n Ultimately, the project is intended to provide a platform for both technological advancement and industrial resilience. By enabling closer collaboration between research institutions, manufacturers and end users, the FAMES pilot line is positioned as a key component of Europe\u2019s strategy to strengthen its semiconductor capabilities and support the next generation of electronic systems.<\/p>\n The announcements set to be made in a few weeks are expected to focus less on infrastructure and more on real-world performance data, ecosystem adoption and early application outcomes, signalling the transition from pilot initiative to a functioning platform for European semiconductor innovation.<\/p>\n","protected":false},"excerpt":{"rendered":"At the upcoming Leti Innovation Days (LID) World Summit later this month, FAMES programme leaders are scheduled to…\n","protected":false},"author":2,"featured_media":1001452,"comment_status":"","ping_status":"","sticky":false,"template":"","format":"standard","meta":{"footnotes":"","_share_on_mastodon":"0"},"categories":[5174],"tags":[38911,2000,299,5187,277904,277903,2343,31167],"class_list":["post-1001451","post","type-post","status-publish","format-standard","has-post-thumbnail","category-eu","tag-electronics","tag-eu","tag-europe","tag-european","tag-fames","tag-pilot-line","tag-research","tag-semiconductors"],"share_on_mastodon":{"url":"https:\/\/pubeurope.com\/@uk\/116683116892727644","error":""},"_links":{"self":[{"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/posts\/1001451","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/comments?post=1001451"}],"version-history":[{"count":0,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/posts\/1001451\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/media\/1001452"}],"wp:attachment":[{"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/media?parent=1001451"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/categories?post=1001451"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.europesays.com\/uk\/wp-json\/wp\/v2\/tags?post=1001451"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}