Samsung Electronics has unveiled its “LPDDR5X-PIM,” a low-power DRAM with built-in AI compute capabilities for smartphones and PCs. The vision is to usher in an era of “thinking memory” that goes beyond simple data storage to perform calculations directly.
South Korea’s Samsung Electronics first showcased the product on August 25 (local time) at Hot Chips 2026, a semiconductor conference held at Stanford University. Hwang Ga-ram, a principal engineer at Samsung Electronics who led the presentation, said, “HBM is currently the de facto standard for AI memory, but as AI evolves toward inference-centric workloads and expands into devices like smartphones and AI PCs, a new memory form factor has become necessary.”
PIM (Processing In Memory) is a technology that embeds small compute units inside memory to handle data storage and computation in a single location. In conventional computer architecture, the processor must fetch data stored in DRAM every time it performs a calculation. As AI models grow larger, the volume of data moving back and forth increases, consuming time and power in the process. PIM partially resolves this bottleneck by performing computation within the memory itself.
Samsung Electronics also disclosed performance figures validated on actual silicon. Testing with Meta’s Llama 3.1 AI model (8 billion parameters) showed that an AI accelerator using conventional low-power memory processed 27 tokens per second, while the same accelerator with LPDDR5X-PIM achieved 81.3 tokens per second—a roughly 3x improvement in throughput. Time to complete the same workload was reduced from 12.3 seconds to 5.4 seconds. The usable bandwidth for in-memory data processing reaches up to 8x that of standard LPDDR5X.
Hwang said, “We are continuing to optimize accuracy and performance, but we expect TPS (tokens per second) to be maintained,” adding that “meaningful results are also emerging in terms of power efficiency.”
Structurally, LPDDR5X-PIM places one PIM compute unit adjacent to each of the 16 memory banks on a single DRAM die—essentially attaching a calculator right next to each data storage region. The design incorporates MAC (multiply-accumulate) units that handle the multiplication and addition operations repeatedly used in AI. The memory takes on repetitive bulk computations over large datasets, while complex calculations are handled by the existing processor.
A point Samsung Electronics particularly emphasized is compatibility with existing systems. LPDDR5X-PIM uses the same 561-ball package as standard LPDDR5X, and employs a technology called Address Alignment Mode (AAM) that allows existing memory controllers’ read/write commands to be leveraged for PIM operations. Standard DRAM sometimes reorders command execution to boost processing speed, but PIM can produce errors if data and operation sequences are misaligned. AAM aligns the data locations used for PIM computation with the addresses the memory actually reads.
This enables a single memory device to operate as standard LPDDR5X when needed, and to activate multiple memory banks simultaneously for PIM operation when AI computation is required. Hwang noted, “The ability to leverage existing systems is a key feature,” explaining that any system using the existing 561-ball LPDDR5X package can swap in the new memory directly without a new memory controller.
This technology is closer to dividing roles with HBM than replacing it. HBM offers high performance but is expensive and power-hungry, making it primarily suited for data centers. LPDDR, by contrast, is low-power memory used in devices like smartphones and AI PCs, positioning it as an alternative for AI inference and on-device applications where cost and power matter. With growing momentum to shrink AI models and run them directly on smartphones, PCs, and edge servers, demand for low-power PIM is expected to rise.
Samsung Electronics first unveiled a concept combining PIM with HBM in 2021. At that time, incorporating compute functionality required sacrificing some memory capacity, but the new LPDDR5X-PIM maintains full memory capacity while adding compute to all 16 banks. The product also received a Next-Generation Memory Award at the Future of Memory and Storage (FMS) conference on August 5.
Meanwhile, at the same conference, Samsung Electronics and SK Hynix also disclosed their next-generation HBM roadmaps. Both companies presented a long-term direction of stacking HBM directly on top of processors such as GPUs. Samsung Electronics outlined a three-stage roadmap that adds more functionality to the base die and ultimately envisions “zHBM”—vertically stacking memory directly on the processor while eliminating the silicon interposer. The company stated this approach could deliver approximately 70% improvement in power efficiency, more than 2.3x increase in DRAM bandwidth, and roughly 100W power savings per DRAM module.
However, stacking memory directly on processors presents thermal management as a core challenge. Even in the consumer processor space, AMD’s Ryzen X3D faced thermal constraints after placing cache memory on top of the processor, limiting clock speed increases in the first generation. The problem could be more severe for power-hungry GPUs or server CPUs. Accordingly, early processor-stacked HBM will likely feature dedicated thermal transfer paths, reduced I/O power, and lower stack heights of around 4 layers rather than 16.